[0021] The specific implementations of the lateral power device with a super junction structure and the manufacturing method provided by the present invention will be described in detail below with reference to the accompanying drawings.
[0022] Reference attachment figure 2 Shown is a schematic diagram of a lateral power device with a super junction structure according to this embodiment, including a P-type support substrate 200, a silicon germanium layer 210 on the surface of the support substrate, and a silicon germanium layer on the surface of the silicon germanium layer. The buried oxide layer 220 and the active layer 230 located on the surface of the buried oxide layer; the active layer includes a gate region 234, a source region 233 and a drain region 237 located on both sides of the gate region 234, and The drift region between the region 234 and the drain region 237; the source region 233 and the drain region 237 are both N-type doped regions; the drift region includes N-type doped regions arranged in a lateral alternating contact manner 236 and P-type doped region 235.
[0023] Wherein, the active layer of the lateral power device with a super junction structure further includes a P-well 231 and a P-type body contact region 232; the P-well 231 is located under the gate region 234; the P-type body contact region 232 Located beside the source region 233 and in contact with the P well 231, it is used to draw out the excess charges accumulated in the P well 231 to avoid floating body effects.
[0024] Reference attachment image 3 What is shown is a schematic diagram of a lateral power device with a super junction structure according to this embodiment. The working principle of the lateral power device with super junction structure provided by the present invention is as follows: silicon germanium (SiGe) and silicon conduction band E c Is there a large band gap difference? E c , The valence band E of silicon germanium (SiGe) and silicon v There is also a band gap difference? E v , Conduction band E c Continuity is much better than valence band E v. In the interface formed by the two, the height of the barrier helps holes to flow from the P-type support substrate to the SiGe, thereby forming a layer of holes on the lower surface of the buried oxide layer, thus avoiding part of the charge in the N-type drift region. Point to the substrate, eliminating the substrate-assisted depletion effect.
[0025] Reference attachment Figure 4 A schematic diagram showing the implementation steps of a method for manufacturing a lateral power device with a super junction structure according to a specific embodiment, including: step S410, providing a first P-type monocrystalline silicon wafer and a second P-type monocrystalline silicon wafer; step S411, using The bonding technology bonds the first P-type silicon wafer and the second P-type silicon wafer together to form a silicon substrate with a buried insulating layer; step S420, implanting germanium ions on the surface of the silicon substrate Forming a silicon germanium layer; step S430, bonding the silicon germanium layer to another silicon wafer; step S440, performing ion implantation on the surface of the silicon substrate to form a drift region; step S441, performing ion implantation on the surface of the silicon substrate Implantation to form a well region; step 442, fabricate a gate region on the surface of the silicon substrate; step 443, ion implantation on the surface of the silicon substrate to form a body contact region and a source region; step 444, ionize on the surface of the silicon substrate The implantation forms the drain region to complete the fabrication of the active layer.
[0026] The following details are attached Figure 5A Attached Figure 5I The method for fabricating a lateral power device with a super junction structure according to this specific embodiment is shown. The manufacturing method of the lateral power device with super junction structure of the present invention at least includes the following steps:
[0027] Reference attachment Figure 5A As shown, referring to step S410, a first P-type monocrystalline silicon wafer 260 and a second P-type monocrystalline silicon wafer 240 are provided, the first P-type monocrystalline silicon wafer 260 and/or the second P-type monocrystalline silicon wafer The surface of 240 has a silicon dioxide layer 220 formed by thermal oxidation. In this specific embodiment, a silicon dioxide layer 220 is formed by thermal oxidation on the surface of the first P-type monocrystalline silicon wafer 260.
[0028] Reference attachment Figure 5B As shown, referring to step S411, the first P-type silicon wafer 260 and the second P-type silicon wafer 240 are bonded together using a bonding technique to form a silicon substrate 250 with a buried insulating layer. And can be annealed at an appropriate temperature to enhance the bonding strength.
[0029] There are many methods for preparing the above-mentioned silicon substrate with buried insulating layer. In addition to the direct bonding of silicon wafers, oxygen injection isolation, smart stripping, epitaxial layer transfer, zone melt recrystallization, and lateral epitaxial growth can also be used. This embodiment is only a preferred step method, and other changes can also be made during specific production. After the above steps S410 and S411 are implemented, a silicon substrate 250 with a buried insulating layer is obtained.
[0030] Reference attachment Figure 5C As shown, referring to step S420, germanium ions are implanted on the surface of the silicon substrate 250 to form a silicon germanium layer 210. Furthermore, the device performance can be enhanced by annealing at an appropriate temperature to avoid lattice damage caused by ion implantation.
[0031] Reference attachment Figure 5D As shown, referring to step S430, the silicon germanium layer 210 is bonded to another P-type silicon wafer to form a P-type supporting substrate 200.
[0032] Reference attachment Figure 5E As shown, referring to step S440, a drift region is formed in the region between the gate region to be formed and the drain region to be formed on the surface of the silicon substrate 250, and alternate contact N-type contacts are formed in the drift region by multiple ion implantation. Doped region 236 and P-type doped region 235. Wherein, phosphorus ion implantation is used to form the N-type doped region 236, and boron ion implantation is used to form the P-type doped region 235.
[0033] In this specific embodiment, only ion implantation is used to form a set of N-type doped regions and P-type doped regions, and multiple sets of N-type doped regions and P-type doped regions can be formed during specific production. This embodiment is only a preferred step method, and other changes can also be made during specific production.
[0034] Reference attachment Figure 5F As shown, referring to step S441, boron ion implantation is performed on the surface of the silicon substrate 250 except for the drift region by ion implantation to form a P well 231.
[0035] Reference attachment Figure 5G As shown, referring to step S442, a gate oxide layer is formed by thermal oxidation, polysilicon is deposited on the gate oxide material, doped to form a polysilicon gate material, and a gate region 234 is formed on the end of the P-well near the drift region.
[0036] Reference attachment Figure 5H As shown, referring to step S443, a P-type body contact region 232 and a source region 233 are formed on the P well 231 by ion implantation. Wherein, boron ion implantation is used to form the P-type body contact region 232, and phosphorus ion implantation is used to form the source region 233.
[0037] Reference attachment Figure 5I As shown, referring to step S444, a drain region 237 is formed on an end of the drift region away from the gate region 234 by phosphorus ion implantation.
[0038] The above-mentioned methods for manufacturing the drift region, the P-well 231, the gate region 234, the source region 233, the body contact region 232, and the drain region 237 all use conventional semiconductor processes such as ion implantation and etching. This embodiment is only a preferred step method. , There can be other changes in the specific production.
[0039] After the above steps S440 to S444 are implemented, the production of the active layer 230 on the surface of the silicon substrate 250 is completed.
[0040] After the above steps S410 to S444 are implemented, the upper surface of the active layer is covered with a field oxide layer, windows are etched on the field oxide layer, and the contact holes of the source region 233, the drain region 237 and the gate region 234 are carved out. Then, the metal is deposited and etched to form the source metal, drain metal and gate metal of the laterally diffused metal oxide semiconductor transistor, and silicon nitride is deposited to form a passivation layer.
[0041] In summary, the present invention provides a lateral power device with a super junction structure and a manufacturing method. The device is based on the energy band theory and is based on the traditional super junction lateral power device with an insulating buried layer. A layer of germanium is implanted on the substrate on the lower surface of the buried layer to form a silicon germanium (SiGe) layer. Due to the large band gap difference between the conduction band of silicon germanium (SiGe) and silicon, the continuity of the conduction band is much better In the price band. In the interface formed by the two, the height of the barrier helps holes to flow from the P-type support substrate to the SiGe, thereby forming a layer of holes on the lower surface of the buried oxide layer, thus avoiding part of the charge in the N-type drift region. Pointing to the substrate eliminates the substrate-assisted depletion effect, that is, avoids the charge imbalance in the drift region, which causes premature breakdown.
[0042] The above are only the preferred embodiments of the present invention. It should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and modifications can be made, and these improvements and modifications should also be considered This is the protection scope of the present invention.
