Low power consumption refresh method of hybrid memory structure

Abstract

The invention provides a low power consumption refresh method of a hybrid memory structure. When a DRAM (Dynamic Random Access Memory) is in a very busy state, a temperature sensitive mode is selected, a storage unit in a nonvolatile memory takes the place of a worst storage unit detected within a present temperature range to reconfigure the DRAM refresh cycle; when the condition that the present temperature is changed to another temperature range at one moment is detected, the information of the worst storage unit is updated, and the refresh cycle is updated; if the DRAM is operated in a temperature non-sensitive mode, the storage unit in the nonvolatile memory takes the place of the detected worst storage unit to reconfigure the refresh cycle of the DRAM; if the operation temperature of the DRAM exceeds a provided value at one moment, the DRAM is switched back to an ordinary refresh mode for a low power consumption refresh mode. By adopting the technical scheme of the invention, the improvement of the refresh cycle is achieved, the refresh power consumption is saved, and the original storage and reading performance of the DRAM is generally not affected.

Description

technical field [0001] The invention belongs to the field of computer hardware and relates to a method for refreshing a memory bar, in particular to a method for refreshing with low power consumption of a hybrid memory structure. Background technique [0002] Over the past few decades, the cost of dynamic random access memory (DRAM) has continued to decrease following Moore's Law. However, as the feature size becomes smaller and smaller, the chip has higher and higher requirements for power consumption. Due to the leakage of the DRAM storage capacitor, it must be refreshed every once in a while. As the capacity of the DRAM becomes larger, the refresh power consumption is also higher. getting bigger, as figure 1 shown. Refresh operations not only consume power, but also degrade DRAM performance due to interference with memory accesses. At present, the DRAM refresh frequency is determined by the worst storage unit (tail bit), for example, 64ms, and the storage unit retentio...

AI Technical Summary

Problems solved by technology

Since DRAM is only used as a cache, the capacity does not need to be large, and PCM does not need to be refreshed regularly when storing data as the main storage medium, so this structure can greatly reduce the power consumption of data storage, but because PCM storage and access speeds are slow, so This structure has a significant drop in overall performance

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