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Package-on-package bonding structure

A stacked packaging and packaging technology, applied in the direction of electrical components, electrical solid devices, circuits, etc.

Active Publication Date: 2017-10-24
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

These relatively new packaging technologies for semiconductors face manufacturing challenges

Method used

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  • Package-on-package bonding structure
  • Package-on-package bonding structure
  • Package-on-package bonding structure

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Embodiment Construction

[0032] The making and using of embodiments of the invention are discussed in detail below. It should be appreciated, however, that the embodiments of the present invention provide many inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are illustrative, not intended to limit the scope of the embodiments.

[0033] Since the invention of the integrated circuit, the semiconductor industry has experienced continuous and rapid development due to the increasing integration of various electronic components (eg, transistors, diodes, resistors, capacitors, etc.). In most cases, this increase in integration is due to the continuous reduction in minimum feature size, allowing more components to be integrated into a given area.

[0034] These integration improvements are essentially two-dimensional (2D) in nature, since the volume occupied by the integrated components is substantially on the surface of the semiconductor wafe...

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Abstract

The present invention provides different embodiments of mechanisms for forming through-package vias (TPVs) with multiple conductive layers and / or recesses in die packages and utilizing TPVs to form package-on-package (PoP) devices with bonded structures . One of the plurality of conductive layers is used as a protective layer for the main conductive layer of the TPV. The protective layer is less prone to oxidation and has a lower formation rate of intermetallic compounds (IMCs) when exposed to solder. The grooves in the TPV of the die package are filled with the solder of the other die package and the IMC layer is formed below the surface of the TPV to strengthen the bonding structure. The present invention provides a package-on-package bonding structure.

Description

[0001] Cross References to Related Applications [0002] This application claims priority to US Provisional Patent Application No. 61 / 746,967, entitled "Package on Package (PoP) Bonding Structures," filed December 28, 2012, the entire contents of which are hereby incorporated by reference. technical field [0003] The present invention relates generally to the field of semiconductors, and more particularly, to package-on-package bonding structures. Background technique [0004] Semiconductor devices are used in a variety of electronic applications such as personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric, conductive, and semiconducting layers of material over a semiconductor substrate and patterning the various material layers using a photolithographic process to form circuit components and elements thereon . [0005] The semiconductor industry...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/538
CPCH01L21/486H01L23/49816H01L23/49827H01L23/5389H01L24/24H01L24/73H01L24/82H01L24/97H01L25/105H01L2224/0401H01L2224/04105H01L2224/12105H01L2224/16225H01L2224/32145H01L2224/32225H01L2224/48227H01L2224/73265H01L2224/97H01L2225/0651H01L2225/06568H01L2225/1035H01L2225/1058H01L2924/12042H01L2924/1305H01L2924/1306H01L2924/13091H01L2924/15311H01L2924/181H01L2924/18162H01L2924/00012H01L2924/00H01L23/12H01L23/48H01L21/4853H01L21/563H01L23/3114H01L23/5384H01L25/50H01L2225/1041
Inventor 林俊成洪瑞斌蔡柏豪
Owner TAIWAN SEMICON MFG CO LTD