Array substrate, display panel and display device
A technology for array substrates and display areas, applied to semiconductor/solid-state device parts, instruments, semiconductor devices, etc., to achieve the effect of reducing width and realizing narrow frame design
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[0024] The core idea of the present invention is that by disposing the capacitor above or below the signal line, the capacitor does not occupy the width of the frame alone, thereby further reducing the width of the frame of the display device and realizing a narrow frame design.
[0025] Embodiment 1 of the present invention provides an array substrate, such as Figure 4 As shown in FIG. 1 , it is a schematic top view structural diagram of the array substrate provided by the embodiment of the present invention. The array substrate provided by the embodiment of the present invention includes: a display area 42 and a non-display area 41, wherein the display area 42 is provided with a plurality of gate lines 421, and a plurality of data lines 422 insulated and intersected with the plurality of gate lines are arranged in opposite A pixel unit adjacent to the area surrounded by the data line and the adjacent gate line includes a TFT 423 as a pixel switch and a pixel electrode 424...
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