Adjustable Duty Cycle Circuit

Abstract

Techniques are disclosed for adjusting and programming the duty cycle of a signal generated by a circuit. In an embodiment, parallel transistors are coupled between a NAND gate and a supply voltage. Selectively enabling the parallel transistors adjusts the switching point of the NAND gate, thereby allowing control of the pulse width of the output signal. In an alternative embodiment, the size of the PMOS versus the NMOS transistors in the NAND gate is selectively varied to achieve the same effect. Further disclosed are applications of the techniques to calibrating the receiver to minimize measured second-order inter-modulation products and / or residual sideband.

Description

[0001] Information about divisional applications [0002] This application is a divisional application of the original Chinese invention patent application titled "Adjustable Duty Cycle Circuit". The application number of the original application is 200880114749.1; the application date of the original application is November 9, 2008; the priority date of the original invention patent application is November 8, 2007. [0003] priority [0004] This application claims the benefit of U.S. Provisional Application No. 60 / 986,397, filed November 8, 2007, entitled "ADJUSTABLEDUTY CYCLE CIRCUIT," the entire disclosure of which is deemed to be the subject of this application. part of the disclosure of the application. technical field [0005] This invention relates to electronic circuits, and more particularly to circuits for generating signals with adjustable duty cycles. Background technique [0006] In the field of electronic circuit design, certain applications require the ...

AI Technical Summary

Problems solved by technology

Inaccuracies in the actual duty cycle can degrade the performance of any given application

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