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Instruction processing system and method

An instruction processing system and instruction technology, applied in the address formation of the next instruction, concurrent instruction execution, electrical digital data processing, etc., can solve the problem that the memory cannot provide instructions for the processor

Active Publication Date: 2014-08-13
SHANGHAI XINHAO MICROELECTRONICS
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] The purpose of the present invention is to provide an instruction processing system and method to solve the problem in the prior art that the first memory / memory with the fastest access speed cannot provide the required instructions to the processor in time

Method used

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  • Instruction processing system and method

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Embodiment Construction

[0120] The instruction processing system and method proposed by the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. Advantages and features of the present invention will be apparent from the following description and claims. It should be noted that all the drawings are in a very simplified form and use imprecise scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.

[0121] Please refer to figure 1 , which is a block diagram of an instruction processing system according to an embodiment of the present invention. Such as figure 1 As shown, the instruction processing system includes a processor 10, an active table 11, a scanner 12, a track table 13, a correlation table 14, a tracker 15, a level 1 cache 16 (ie the first memory , that is, the memory with the highest storage speed) and a secondary cache 17 (ie, the second ...

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Abstract

An instruction processing system is provided. The system includes a central processing unit (CPU), an m number of memory devices and an instruction control unit. The CPU is capable of being coupled to the m number of memory devices. Further, the CPU is configured to execute one or more instructions of the executable instructions. The m number of memory devices with different access speeds are configured to store the instructions, where m is a natural number greater than 1. The instruction control unit is configured to, based on a track address of a target instruction of a branch instruction stored in a track table, control a memory with a lower speed to provide the instruction for a memory with a higher speed.

Description

technical field [0001] The invention relates to the technical field of computer architecture, in particular to an instruction processing system. Background technique [0002] In today's computer architecture, the processor is its core device, and the processor includes a general processor (General Processor), a central processing unit (CPU), a microcontroller (MCU), a digital signal processor (DSP), an image Processor (GPU), System on Chip (SOC), Application Specific Integrated Circuit (ASIC), etc. Through the operation of the processor, various computing tasks can be solved. Generally, a processor needs to read and execute a large number of instructions during operation, thus, a memory is required to store these instructions. [0003] An existing instruction processing system usually includes a processor and a multi-level memory system, and the multi-level memory system usually includes a plurality of memories with different access speeds. Taking a secondary memory syste...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/38
CPCG06F9/32G06F9/3804
Inventor 林正浩
Owner SHANGHAI XINHAO MICROELECTRONICS
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