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Precision exception signaling for multiple data architecture

A multi-data and abnormal technology, applied in the direction of electrical digital data processing, instrumentation, error detection/correction, etc., can solve problems such as delay processing

Inactive Publication Date: 2014-08-27
MIPS TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, when the exception handler cannot discern which data input caused the exception, processing of the exception typically also delays processing of data not associated with the exception

Method used

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  • Precision exception signaling for multiple data architecture
  • Precision exception signaling for multiple data architecture
  • Precision exception signaling for multiple data architecture

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Embodiment Construction

[0015] The following detailed description of embodiments of the present invention will be made with reference to the accompanying drawings that illustrate exemplary embodiments. Embodiments described herein relate to low power multiprocessors. Other embodiments are possible, and modifications can be made within the spirit and scope of this description. Therefore, the detailed description is not intended to limit the embodiments described below.

[0016] It should be apparent to those skilled in the relevant art that the embodiments described below can be implemented in many different embodiments of software, hardware, firmware and / or entities illustrated in the figures. Any actual software code implementing an embodiment with dedicated control of hardware is not intended to limit the description. Accordingly, the operational behavior of the described embodiments should be understood as modifications and variations from the described embodiments may exist, given the degree of...

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Abstract

Methods and systems that perform one or more operations on a plurality of elements using a multiple data processing element processor are provided. An input vector comprising a plurality of elements is received by a processor. The processor determines if performing a first operation on a first element will cause an exception and if so, writes an indication of the exception caused by the first operation to a first portion of an output vector stored in an output register. A second operation can be performed on a second element with the result of the second operation being written to a second portion of the output vector stored in the output register.

Description

technical field [0001] The present invention generally relates to systems and methods for performing one or more operations on one or more elements utilizing a multi-data processing unit processor. Background technique [0002] Multiple data processing unit processors, such as Single Instruction Multiple Data (SIMD) or Multiple Instruction Multiple Data (MIMD), receive multiple data inputs, operate on the input data, and output the results of the operations to, for example, output registers. For example, such a processor might take inputs a, b, c, and d, and add them together to produce a result of a+b and c+d. Sometimes it is problematic for the processor to perform a specified operation on one or more data inputs and an exception is raised. This happens, for example, when the specified operation is not for the processor to perform on the input provided. In this scenario, the processor will not be able to perform the operation and an exception will be generated. [0003]...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/00
CPCG06F9/30G06F9/3001G06F9/30036G06F9/3861
Inventor I·盖巴西亚J·罗宾森
Owner MIPS TECH INC
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