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Semiconductor device

A semiconductor and conductor layer technology, applied in semiconductor devices, semiconductor/solid-state device parts, electric solid-state devices, etc., can solve problems such as difficult metal wire space and encapsulation enlargement

Inactive Publication Date: 2014-09-17
KK TOSHIBA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, in such a semiconductor device, the area occupied by the semiconductor chip is enlarged (wide), so it is difficult to secure a space for placing metal lines in the package
Also, if you want to secure space for placing metal lines inside the package, the package will increase

Method used

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  • Semiconductor device
  • Semiconductor device
  • Semiconductor device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment approach ）

[0025] figure 1 It is a plan view of the semiconductor device 100 according to the first embodiment. figure 2 It is a partially enlarged cross-sectional view of the semiconductor device 100 according to the first embodiment. In this embodiment, the semiconductor device 100 is a TOSP (Thin Small Outline Package, Thin Small Outline Package) type semiconductor device.

[0026] Such as figure 1 , figure 2 As shown, the semiconductor device 100 includes a lead substrate 110 , semiconductor chips 121 to 124 , spacers 130 , wires 140 , and sealing resin 150 . again, in figure 1 In , the semiconductor chips 121 to 124 sealed with the sealing resin 150 , the spacers 130 , and the wires 140 are described by solid lines instead of broken lines.

[0027] The lead substrate 110 has a plurality of leads 111 . A metal material having excellent electrical conductivity, such as copper (Cu), iron (Fe), and nickel (Ni), is used for each lead 111 . Each lead 111 has an inner lead 111A se...

no. 2 approach ）

[0057] Figure 6 It is a plan view of the semiconductor device 200 according to the second embodiment. Figure 7 It is a partially enlarged cross-sectional view of the semiconductor device 200 according to the second embodiment. In this embodiment, the semiconductor device 200 is a TSOP type semiconductor device.

[0058] Such as Figure 6 , Figure 7 As shown, the semiconductor device 200 includes a lead substrate 210 , semiconductor chips 221 to 224 , a spacer 230 , and a sealing resin 250 . again, in Figure 6 In , the semiconductor chips 221 to 224 and the spacer 230 sealed by the sealing resin 250 are described by solid lines instead of broken lines.

[0059] The lead substrate 210 has a plurality of leads 211 . For each lead 211, a metal material having excellent electrical conductivity such as copper and / or iron or nickel is used. Each lead 211 has an inner lead 211A sealed in the sealing resin 250 and an outer lead 211B exposed from the sealing resin 250 . The ...

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Abstract

The invention provides a semiconductor device which can connect inner wires in a continuously-minimized and high-density semiconductor device. The device disclosed in the embodiment comprises a plurality of wires, which are divided into inner wires and outer wires; a semiconductor chip, which is arranged on the plurality of wires; a partition member, which is arranged between the semiconductor chip and the plurality of wires, wherein a gap is formed between the back of the semiconductor chip and the plurality of wires; and a lead wire, which is arranged in the gap and electrically connects the inner wires under the back of the semiconductor chip.

Description

[0001] This application enjoys priority based on Japanese Patent Application No. 2013-53387 (application date: March 15, 2013) and Japanese Patent Application No. 2013-58016 (application date: March 21, 2013). This application incorporates these prior applications in their entirety by reference. technical field [0002] Embodiments of the present invention relate to semiconductor devices. Background technique [0003] As the speed of semiconductor devices increases, they are more likely to be affected by potential changes in power supply (Vcc) and ground (Vss). In particular, data I / O signals are affected by potential changes in power supply, ground, or both, and the I / O signals fluctuate greatly in rising / falling portions. Then, for the purpose of stabilizing (strengthening) the potential of the power supply and the ground or reducing the inductance between the power supply and the ground, the leads for the power supply and the leads for the ground (ground) are electricall...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/528
CPCH01L2224/48091H01L2224/73265H01L2224/48227H01L2224/48145H01L2224/48147H01L2924/00014H01L2924/00012
Inventor 石井齐
Owner KK TOSHIBA