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A method for calculating the testability index of a board-level circuit

A technology of index calculation and board-level circuit, applied in the direction of calculation, electrical digital data processing, special data processing application, etc., can solve the problem of not reflecting the relationship between the test and the fault location, and the inability to calculate the testability index.

Inactive Publication Date: 2017-01-18
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Abstract
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AI Technical Summary

Problems solved by technology

Compared with the multi-signal flow method, the matrix D u It does not reflect the positional relationship between tests and faults. In addition, due to the many-to-many relationship between tests and faults, testability indicators (such as fault isolation) cannot be directly calculated based on this matrix
In addition, the same test has different test coverage for different chips (or modules), and different tests have different test coverage for the same chip. How to optimize this many-to-many relationship with different fault coverage is another problem

Method used

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  • A method for calculating the testability index of a board-level circuit
  • A method for calculating the testability index of a board-level circuit
  • A method for calculating the testability index of a board-level circuit

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Embodiment Construction

[0031] Specific embodiments of the present invention will be described below in conjunction with the accompanying drawings, so that those skilled in the art can better understand the present invention. It should be noted that in the following description, when detailed descriptions of known functions and designs may dilute the main content of the present invention, these descriptions will be omitted here.

[0032] figure 1 It is a schematic flow chart of the specific implementation of the board-level circuit testability index calculation method of the present invention. Such as figure 1 As shown, the method for calculating the testability index of the board-level circuit of the present invention includes the following steps:

[0033] S101: Construct a dependency matrix D independent of signal flow u :

[0034] According to the test information database, including device types, failure probability of various devices, failure modes, probability of each failure mode, test ite...

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Abstract

The invention discloses a method for calculating the testability index of a board-level circuit. According to the test information database and combined with the device information in the circuit, a dependency matrix Du independent of signal flow and position is constructed, and the highest fault detection rate is obtained by calculating the dependency matrix Du. Then the dependency matrix Du is reconstructed to obtain the reconstruction matrix, which realizes the isolation of devices in different positions in the same type of devices, and the highest fault isolation rate is calculated according to the reconstruction matrix, and the fault isolation rate of the current test selection is calculated according to the Boolean vector selected by the test. It can be seen that the present invention realizes the calculation of various testability indicators in the board-level circuit through the construction and reconstruction of the dependency matrix Du which is not related to the signal flow.

Description

technical field [0001] The invention belongs to the technical field of board-level circuit fault testing, and more specifically relates to a method for calculating testability indexes of board-level circuits. Background technique [0002] The system-level testability indicators of board-level circuits include commonly used data in board-level circuit testing, including the highest fault detection rate (FDR), the highest fault isolation rate (FIR), and the fault isolation rate of the currently selected test. Most of the commonly used system-level testability index calculation methods are based on the dependency matrix (D matrix). The D matrix is ​​obtained from the multi-signal flow diagram of the system under test, which reflects the relationship between signal flow, test and failure modes, failure modes, and high-order dependencies between tests. The general process of obtaining the D matrix is: manually establish a multi-signal flow diagram, generate high-order dependenci...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F19/00
Inventor 杨成林田书林刘震龙兵
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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