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Ethernet switch FPGA verification method based on UVM verification method

A verification method and Ethernet technology, applied in the field of Ethernet switch FPGA verification, can solve problems such as low degree of automation operation, reduce workload, realize automatic execution, and improve development efficiency and quality.

Inactive Publication Date: 2014-09-24
INSPUR GROUP CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

FPGA developers generally use Windows PCs to operate the software through a graphical interface, with a low degree of automation

Method used

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Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0014] The Ethernet switch FPGA verification method based on the UVM verification method is realized by three parts: the main body of the UVM verification platform, the measured object of the four-port Ethernet switch, and the SystemC reference model of the Ethernet switch. The SystemC reference model of the object under test and the Ethernet switch sends Ethernet packets, and collects the packets returned from the object under test of the Ethernet switch and the SystemC reference model of the Ethernet switch, compares whether they are the same, and judges the status of the object under test. Whether the behavior is correct; the logical behavior of the SystemC reference model of the Ethernet switch is consistent with the test object of the Ethernet switch, but the details of timing are ignored; the logic of the test object of the Ethernet switch is downloaded to the FPGA after the simulation verification is completed. work in the environment.

[0015] The implementation method...

Embodiment 2

[0017] The Ethernet switch FPGA verification method based on the UVM verification method is realized by three parts: the main body of the UVM verification platform, the measured object of the four-port Ethernet switch, and the SystemC reference model of the Ethernet switch. The SystemC reference model of the object under test and the Ethernet switch sends Ethernet packets, and at the same time sends and receives IP packets and ARP packets of the third-layer protocol. The third-layer protocol packets are packaged in the second-layer protocol. High-level messages are also packaged layer by layer; in order to use the UVM verification method to realize the verification of this layered protocol, a conversion sequence is established in the verification environment (continuously read the sequence item from the sequencer of the ipv4 agent, and convert it to the Ethernet's sequence item and send it to the ethernet sequencer), the conversion sequence needs to keep running to convert the ...

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Abstract

The present invention discloses an Ethernet switch FPGA verification method based on a UVM verification method. The method is realized by a UVM verification platform main body, a tested object of a four-port Ethernet switch and a reference model of the Ethernet switch. The UVM verification platform main body sends messages to the tested object of the four-port Ethernet switch and the reference model of the Ethernet switch simultaneously, and collects the messages returned from the tested object of the Ethernet switch and the reference model of the Ethernet switch, compares whether the messages are same, and judges whether the behavior of the tested object is correct. The tested object logic of an Ethernet switch is downloaded to an FPGA and works in a real environment after being simulated and verified. The Ethernet switch FPGA verification method based on the UVM verification method of the present invention realizes the automatic execution of the FPGA logic verification, and enables the development efficiency and quality of the FPGA logical codes to be improved and the later debugging on-board workload to be reduced.

Description

technical field [0001] The invention relates to the fields of Ethernet communication and logic verification, in particular to an Ethernet switch FPGA verification method based on a UVM verification method. Background technique [0002] Ethernet (Ethernet) is a computer local area network networking technology. The IEEE 802.3 standard formulated by IEEE provides the technical standard of Ethernet. It specifies the content of the connection including physical layer, electrical signal and media access layer protocol. Ethernet is currently the most widely used LAN technology. [0003] Ethernet switches are important components in Ethernet communications. After the switch is powered on, it first forwards all received data to all ports. Next, when it learns the address of each port, it only sends non-broadcast data to the specific destination port. In this way, Ethernet switching can be realized between any port pairs, and the communication between all port pairs does not int...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L12/26H04L12/24H04L12/933
Inventor 耿介梁智豪毕研山
Owner INSPUR GROUP CO LTD
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