Device and method for scheduling and buffering data packets

Abstract

The invention discloses a data packet scheduling and caching device, comprising: packet data first-in-first-out (FIFO) module, packet header data FIFO module and business processing module; wherein, the packet data FIFO module is used for scheduling and reading data packet data At the same time, extract the packet header information of the data packet, and send the packet header information to the packet header data FIFO module for storage; it is also used to schedule and read the packet tail mark, and obtain the packet length information and the cyclic redundancy check code (CRC) check result The packet header data FIFO module is used to store header information; when the packet data FIFO module reads the packet tail sign corresponding to the packet header information, reads the packet header information; the business processing module is used for according to the packet header information and the packet length information and CRC check results to generate descriptor information. The invention also discloses a data packet scheduling and caching method at the same time. By adopting the invention, a large number of chip internal storage resources can be saved, the delay of data packets in the chip can be shortened, the cost of the chip can be reduced, and the area and power consumption of the chip can be improved. .

Description

technical field [0001] The invention relates to the field of data communication, in particular to a device and method for scheduling and buffering data packets. Background technique [0002] At present, in the traditional traffic management chip, for the business processing of data packets, it is necessary to determine the data packet needs according to the packet header information, packet length information and cyclic redundancy check code (CRC, Cyclic Redundancy Check) check result of the data packet. No cache is required. Both the packet length information and the CRC check result can only be calculated after receiving the complete data packet, that is to say, they can only be obtained at the end of the packet. [0003] In practical applications, it is usually necessary to open up a port data first-in-first-out (FIFO, First In First Out) memory for each input port to store at least one complete data packet, extract packet header information and obtain packet length info...

AI Technical Summary

Problems solved by technology

With the rapid growth of network services, the number of input ports of traffic management chips is increasing, and the length of data packets is getting larger and larger, and the requirements for chip storage capabilities are also getting higher and higher, which in turn increases the cost of chips

[0004] In addition, after the data packets are processed by predetermined rules in the business processing module, tens or even hundreds of bytes of descriptor information will be generated. The descriptor information is usually stored inside the traffic management chip, which invisibly increases the storage capacity of the chip. burden

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