A three-dimensional integrated circuit on-chip network routing method and system thereof

An integrated circuit and on-chip network technology, which is applied in the field of 3D integrated circuit on-chip network routing, can solve the problems of on-chip network communication performance, low system overhead of steering restrictions, etc., and achieves the effect of avoiding additional overhead, improving fairness, and loosening 3D steering restrictions.

Active Publication Date: 2017-10-27
INST OF COMPUTING TECH CHINESE ACAD OF SCI
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Problems solved by technology

[0007] The purpose of the present invention is to provide a routing method and system for a three-dimensional integrated circuit on-chip network to solve the conflicting problems of on-chip network communication performance, steering restrictions and lower system overhead in the prior art

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  • A three-dimensional integrated circuit on-chip network routing method and system thereof
  • A three-dimensional integrated circuit on-chip network routing method and system thereof
  • A three-dimensional integrated circuit on-chip network routing method and system thereof

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Embodiment Construction

[0048] The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments, but not as a limitation of the present invention.

[0049] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0050] The object of the present invention is to provide a routing method for a three-dimensional integrated circuit on-chip network guided by a fair steering model. It can balance high communication performance and low system overhead on a three-dimensional integrated circuit on-chip network.

[0051] The invention provides a routing method of a three-dimensional integrated circuit on-chip network guided by a fair steering model, generally speaking, a one-way communication process in which a source node routes data packets to a destination node. Define the source node as S (Source) node, and the destination node as D (Destination) node. Key points of the pre...

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Abstract

The invention discloses a routing method for a three-dimensional integrated circuit on-chip network. The method adopts a three-dimensional steering model for routing guidance, and adopts a port selection mechanism for legal output port selection, and unidirectionally routes data packets from a source node to a destination node. The three-dimensional steering model is based on the odd-even steering model, using the X-Y plane or X-Z plane or Y-Z plane in the three-dimensional scene as the reference plane, and mapping the routing path between the source node and the destination node to the reference plane, And by adopting the principle of illegal steering between layers of the device layer on the reference plane, and the corresponding supplementary principles to restrict the steering. The invention also discloses a routing system of the three-dimensional integrated circuit on-chip network.

Description

technical field [0001] The invention relates to the design field of integrated circuits, in particular to a three-dimensional integrated circuit on-chip network routing method guided by a fair steering model. Background technique [0002] Three-dimensional integration technology is a packaging technology that stacks different device layers of a chip and vertically integrates them together. The title of the packaging technology in the journal is: "proceedings of the IEEE, Volume: 89, Issue: 5, 2001, pp.602-633.", and the title of the document is: "3-D ICs: a novel chip design for improving deep- Submicrometer interconnect performance and systems-on-chip integration," authored by: Banerjee K. et al., disclosed that this technology can shorten the physical connection length in the chip and reduce system delay and power consumption. figure 1 It is a schematic diagram of a simple 4*2*3 three-dimensional chip-on-chip network, and the topology is a three-dimensional Mesh structure...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L12/771H04L12/935H04L45/60H04L49/111
Inventor 周君李华伟李晓维
Owner INST OF COMPUTING TECH CHINESE ACAD OF SCI
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