Unlock instant, AI-driven research and patent intelligence for your innovation.

Test Structure and Test Method of Transistor Overlap Capacitance

A technology of test structure and test method, which is applied in the direction of semiconductor/solid-state device test/measurement, circuit, electrical components, etc., can solve the problem that it is difficult to accurately eliminate the influence of semiconductor devices with overlapping capacitance, it is difficult to accurately obtain the value of overlapping capacitance, and the testing method of overlapping capacitance Complicated issues

Active Publication Date: 2017-02-22
SEMICON MFG INT (SHANGHAI) CORP
View PDF9 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] The problem solved by the present invention is that the overlapping capacitance test method of transistors in the prior art is complicated, and it is difficult to accurately obtain the value of the overlapping capacitance, which makes it difficult to accurately eliminate the influence of the overlapping capacitance on the semiconductor device

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Test Structure and Test Method of Transistor Overlap Capacitance
  • Test Structure and Test Method of Transistor Overlap Capacitance
  • Test Structure and Test Method of Transistor Overlap Capacitance

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0049] refer to Figure 4 , execute step S1 to provide a test structure 300 .

[0050] The test structure 300 includes a transistor 310 on a substrate 301 , a first connection structure 311 and a second connection structure 312 . The transistor 310 includes a gate dielectric layer 314 on the substrate 301 , a gate 315 on the gate dielectric layer 314 , and a source region 316 and a drain region 317 in the substrate 301 on both sides of the gate 315 . The first connection structure 311 is located on the surface of the source region 316 and connected to the source region 316 , and the second connection structure 312 is located on the surface of the drain region 317 and connected to the drain region 317 . Wherein, the source region 316 or the drain region 317 also includes an overlapping region under the gate dielectric layer 314 , that is to say, the overlapping region only exists in the substrate on one side of the gate 315 . In this embodiment, the drain region 317 includes ...

no. 2 example

[0067] In the second embodiment, the test structure 500 includes two or more transistors 510 .

[0068] refer to Figure 6 , Figure 6 is a top view of the test structure in the second embodiment. The test structure 500 includes two or more transistors 510 arranged side by side on a substrate 501 . The gate 511 of the transistor 510 is striped in the gate line direction (XX' direction). The first connection structure 512 located on the source region (not shown) on one side of the gate 511, and the second connection structure 513 on the drain region (not shown) on the other side. lower overlap region (not shown). Electrically connect a plurality of gates 511 to the first test terminal A; electrically connect a plurality of first connection structures 512 to a second test terminal B; electrically connect a plurality of second connection structures 513 , connected to the third test terminal C.

[0069] Continue to refer to Figure 6 , in this embodiment, the source region ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

Provided is a test structure for transistor overlap capacitance and a test method thereof. The test method of transistor overlap capacitance comprises the steps that the test structure is provided. The test structure comprises a transistor, a first connecting structure and a second connecting structure which are arranged on a semiconductor substrate. The transistor comprises a gate dielectric layer which is arranged on the substrate, a gate electrode which is arranged on the gate dielectric layer, and a source region and a drain region which are arranged in the semiconductor substrate of the two sides of the gate electrode. The first connecting structure is arranged on the surface of the source region and connected with the source region. The second connecting structure is arranged on the surface of the drain region and connected with the drain region. The source region or the drain region also comprises an overlap region which is arranged below the gate dielectric layer. First capacitance between the first connecting structure and the gate electrode is acquired via testing. Second capacitance between the second connecting structure and the gate electrode is acquired via testing. An absolute value of difference of first capacitance and second capacitance is calculated so that overlap capacitance of the transistor is obtained. The test method of transistor overlap capacitance is simple, and overlap capacitance of the transistor can be accurately and simply tested.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a test structure and a test method for transistor overlap capacitance. Background technique [0002] In the existing semiconductor technology field, transistors are one of the basic components of integrated circuits and are widely used. The performance of transistors directly affects the performance of the entire integrated circuit. Therefore, in the prior art, the work effect of the integrated circuit including the transistor is improved more by improving the performance of the transistor. [0003] refer to figure 1 , figure 1 It is a schematic cross-sectional structure diagram of a semiconductor device including a transistor in the prior art, including: a semiconductor substrate 100; a gate dielectric layer 101 on the semiconductor substrate 100 and a gate 102 on the gate dielectric layer 101; around the gate 102 The side wall 103 on the semiconductor substrate 100; t...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/544H01L21/66
Inventor 李勇洪中山
Owner SEMICON MFG INT (SHANGHAI) CORP