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FPGA configuration file upgrading method and system

A technology for configuring files and upgrading files, which is applied in the direction of program control devices, program loading/starting, etc., and can solve problems such as increasing hardware costs and adding third-party devices

Active Publication Date: 2014-11-26
RUIJIE NETWORKS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, both of the above two methods need to add third-party devices for FPGA upgrade, which increases the hardware cost

Method used

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  • FPGA configuration file upgrading method and system
  • FPGA configuration file upgrading method and system
  • FPGA configuration file upgrading method and system

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Embodiment Construction

[0051] Ferroelectric memory is a non-volatile memory with a special process, which uses artificially synthesized lead-zirconium-titanium (PZT) materials to form memory crystals. When an electric field is applied to the ferrotransistor, the central atom follows the field and stops at the low-energy state I. Conversely, when an electric field reversal is applied to the same ferrotransistor, the central atom moves in the crystal along the direction of the electric field and stops. In another low energy state II position. A large number of central atoms move and couple in the crystal unit cell to form ferroelectric domains, and the ferroelectric domains form polarized charges under the action of an electric field. The polarization charge formed by the ferroelectric domain reversal under the electric field is higher, and the polarization charge formed by the ferroelectric domain without reversal under the electric field is lower. The binary stable state of this ferroelectric materi...

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Abstract

The invention discloses an FPGA configuration file upgrading method and system which are used for upgrading FPGA configuration files and lowering the hardware cost for upgrading of the FPGA configuration files on the premise of not adding logic devices. The method includes the steps of receiving configuration upgrading file fragments, determining a first storage of a currently loaded configuration file, controlling a second state retainer in a second configuration unit to switch a second electronic switch to a configuration file upgrading access, writing the received configuration upgrading file fragments into a second storage, adding a fragment to a write address of the second storage, judging whether all the configuration upgrading file fragments are received or not, if yes, switching the second electronic switch to the configuration file upgrading access and closing the configuration file upgrading access of the first electronic switch, and if not, receiving a next configuration upgrading file fragment and carrying out the step of writing the received configuration upgrading file fragment into the second storage.

Description

technical field [0001] The invention relates to the technical field of electronic circuit design, in particular to an FPGA configuration file upgrading method and system. Background technique [0002] FPGA is a new type of high-performance programmable chip with high integration. Its internal circuit function is programmable (Programmable). It is suitable for high-speed, high-density high-end digital logic circuit design. It allows the designer to use the hardware description language to complete the circuit design, and generate the configuration file by compiling the corresponding synthesis tool. After the FPGA loads the configuration file, it can realize the logic function required by the design. [0003] The way FPGA loads the configuration file is shown in Table 1: [0004] Table 1 [0005] [0006] Among them, JTAG is usually the loading method in debug mode, which is used for online debugging of FPGA. Master serial / SPI and Master SelectMAP / BPI are for the FPGA t...

Claims

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Application Information

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IPC IPC(8): G06F9/445
Inventor 陈鹏
Owner RUIJIE NETWORKS CO LTD
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