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Semiconductor device
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A technology of semiconductors and wires, applied in the field of semiconductor devices, can solve problems such as changes in electrical characteristics and low adhesion, and achieve the effect of improving reliability
Active Publication Date: 2018-12-18
RENESAS ELECTRONICS CORP
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[0008] However, since the surface of the terminal has low adhesion to the resin, if a large load (stress, damage) is applied to the joint portion (joint region) of the conductive member on the surface of the terminal, the electrical Changes in characteristics (and even disconnection)
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Embodiment approach 1
[0099]
[0100] Figure 1 ~ Figure 3 is a plan view of the semiconductor device PKG of the present embodiment, Figure 4 is a cross-sectional view of the PKG of the semiconductor device, Figure 5 is a partially enlarged cross-sectional view of the PKG of the semiconductor device, Figure 6 is a partially enlarged plan view of the PKG of the semiconductor device, Figure 7 is a partially enlarged cross-sectional view of the PKG of the semiconductor device.
[0101] Figure 1 ~ Figure 3 middle, figure 1 A plan view (ie, a top view) showing the upper surface side of the semiconductor device PKG, figure 2 A plan view (that is, a bottom view) of the lower surface side of the semiconductor device PKG is shown. image 3 It is a plan view (that is, a top view) of the upper surface side of the semiconductor device PKG, and shows a plan view perspective view through which the sealing body MR is seen. In addition, in image 3 In the figure, in order to easily understand the p...
Embodiment approach 2
[0360] Figure 54 and Figure 55 is an explanatory diagram of a semiconductor device according to Embodiment 2, Figure 54 Corresponding to the above-mentioned first embodiment Figure 6 . which is, Figure 54 It is a plan view showing the exposed surface EX of the terminal TE exposed from the through-hole SH of the base material BS and the lead wire BW connected thereto. Figure 55 corresponds to and Figure 54 A top view of the same area, Figure 55 Indicates the stage just before the lead wire BW is connected to the exposed surface EX of the terminal TE.
[0361] In Embodiment 1 described above, the bump SB formed on the exposed surface EX of the terminal TE is used as the fixing means provided on the exposed surface EX of the terminal TE. In this Embodiment 2, if Figure 54 and Figure 55 As shown, as the fixing means provided on the exposed surface EX of the terminal TE, a concave portion (recessed portion) 81 formed on the exposed surface EX of the terminal TE i...
Embodiment approach 3
[0374] Figure 61 and Figure 62 is an explanatory diagram of a semiconductor device according to Embodiment 3, Figure 61 Corresponding to the above-mentioned first embodiment Figure 6 . which is, Figure 61 It is a plan view showing the exposed surface EX of the terminal TE exposed from the through-hole SH of the base material BS and the lead wire BW connected thereto. Figure 62 corresponds to and Figure 61 A top view of the same area, Figure 62 Indicates the stage just before the lead wire BW is connected to the exposed surface EX of the terminal TE. in addition, Figure 61 and Figure 62 Although it is a top view, the regions 71 and 72 are hatched in different directions so that the regions 71 and 72 on the exposed surface EX of the terminal TE can be easily distinguished.
[0375] In the first embodiment described above, as the fixing means provided on the exposed surface EX of the terminal TE, the bump SB formed on the exposed surface EX of the terminal TE i...
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Abstract
A semiconductor device (PKG) capable of improving reliability of the semiconductor device. Including an insulating base material (BS) having a through hole (SH), a terminal (TE) formed on the lower surface (BSb) of the base material (BS), and a terminal (TE) mounted on the upper surface of the base material in a face-up manner Semiconductorchip (CP) on (BSa). In addition, it has electrical conductivity such as a wire (BW) that electrically connects the exposed surface (EX) of the terminal (TE) exposed from the through hole (SH) of the base material (BS) to the pad (PD) of the semiconductorchip (CP). A member, and a sealing body (MR) that seals the conductive member, the inside of the through-hole (SH) of the base material (BS), and the semiconductor chip (CP). The exposed surface (EX) of the terminal (TE) exposed from the through-hole (SH) of the base material (BS) is provided with a fixing unit in a region other than the bonding portion of a conductive member such as a bonding wire (BW).
Description
technical field [0001] The present invention relates to a semiconductor device, and is applicable to, for example, a semiconductor device including a semiconductor chip. Background technique [0002] There is a technique of obtaining an IC card capable of data communication with the outside by incorporating a semiconductor device in a card body. [0003] JP 2011-210936 A (Patent Document 1) describes a technique related to a semiconductor device incorporated in an IC card. [0004] prior art literature [0005] patent documents [0006] Patent Document 1: Japanese Patent Laid-Open No. 2011-210936 [0007] For example, in the so-called COT (Chip On Tape) package in which a semiconductor chip is mounted on a base material made of a tape as in the above-mentioned Patent Document 1, through holes formed in the base material, on the back surface of the base material Conductive members (conductive wires in the aforementioned Patent Document 1) are connected to the surface of t...
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