Virtualization electrical characteristic optimization test (VTRIM) method

A test method and technology of electrical characteristics, applied in the field of virtualized electrical characteristics optimization test, can solve problems such as long test time, and achieve the effect of solving many limitations of test equipment and solving low test efficiency

Active Publication Date: 2014-12-24
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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Problems solved by technology

This test method requires a relatively long test time. Taking the 5-digit digital parameter (DAC) as an example, the above (1)-(3) process needs to be repeated 32 (that is, 25) times, and fi

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  • Virtualization electrical characteristic optimization test (VTRIM) method
  • Virtualization electrical characteristic optimization test (VTRIM) method

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Embodiment Construction

[0010] The process of the virtualized electrical characteristic optimization test (VTRIM) method of the present invention is as follows:

[0011] 1. Historical data modeling

[0012] Taking the case of the linear fitting function as an example, firstly, the measured analog values ​​(electrical optimization parameters such as voltage value, current value, frequency value, etc., including at least one of the parameters) measured by all debug sample chips are fitted into the linear function of each chip y=ax+b, where x represents a digital parameter (DAC) value and y represents a measured value of an electrical optimization parameter. Then, based on the slope data (a 1 ,...a q ) Calculate the standard deviation σ of the sample, and estimate the process float Δ according to the data of the process characteristic parameter (PCM) (generally, the device resistance, capacitance, and leakage current value that affects the electrical parameters), and complete the distribution verifica...

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Abstract

The invention discloses a virtualization electrical characteristic optimization test (VTRIM) method. The test method includes the process of 1), collecting and debugging analogue values and process characteristic parameters of sample chips and establishing function models best matched with acquired data; 2), determining the number of samples needing to be collected for modeling in a mass production test according to a confidence interval; during the mass production test, collecting the data of the chips of the samples with the determined number, and establishing the best function of the virtualization electrical characteristic optimization test through a mathematical optimization method; 4), according to the step 3), establishing the best function and completing the virtualization electrical characteristic optimization test of all the chips. The best function of the data is searched by establishing the data model of the electrical characteristic optimization test (TRIM) of a product, the virtualization electrical characteristic optimization test of all the chips is completed according to the function in the mass production test process, and rapid and reliable optimization of the electrical characteristic parameters of all the chips of an entire wafer is realized.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit testing, in particular to a virtualized electrical characteristic optimization testing (VTRIM) method. Background technique [0002] The process of testing the chip by the general electrical characteristic optimization test (TRIM) method is: (1) set the digital parameter (DAC) to the chip; (2) measure the chip output analog value (voltage, current or frequency, etc.); (3) compare and judge the measurement Whether the value is within the design range. This test method requires a relatively long test time. Taking the 5-digit digital parameter (DAC) as an example, the above (1)-(3) process needs to be repeated for 32 (that is, 2 5 ) times, the final test program selects the digital parameter (DAC) corresponding to the output analog value that best matches the design range as the best digital parameter (BESTDAC) setting. Contents of the invention [0003] The technical problem to be...

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Application Information

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IPC IPC(8): G06F17/50
Inventor 宋旻皓陈斌斌
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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