Management method for instruction cache and processor

Abstract

The embodiment of the invention provides a management method for an instruction cache and a processor, relates to the field of computers, and aims to expand the instruction cache capacity of a hardware thread, lower the missing rate of the instruction cache and enhance the system performance. A hardware thread identifier in a shared instruction cache of the processor is used for identifying a hardware thread which corresponds to a cache line in the shared instruction cache; a private instruction cache is used for storing an instruction cache line substituted from the shared instruction cache; a missing cache is further provided. The method comprises the following steps: when the hardware thread of the processor acquires an instruction from the instruction cache, accessing the shared instruction cache in the instruction cache and the private instruction cache which corresponds to the hardware thread simultaneously; determining the existence of an instruction in the shared instruction cache and the private instruction cache which corresponds to the hardware thread, and acquiring the instruction from the shared instruction cache and the private instruction cache which corresponds to the hardware thread according to a judgment result. The embodiment of the invention is used for managing the instruction cache of the processor.

Description

technical field [0001] The invention relates to the field of computers, in particular to an instruction cache management method and a processor. Background technique [0002] CPU (Central Processing Unit, central processing unit) cache (Cache Memory) is a temporary storage located between the CPU and the memory, and its capacity is much smaller than that of the memory. CPU read speed. [0003] In a multi-threaded processor, multiple hardware threads obtain instructions from the same I-Cache (instruction cache). When there is no instruction to be obtained in the I-Cache, while sending a missing request to the next-level Cache, Switching to other hardware threads to access the I-Cache continues to fetch instructions, reducing the pause of the pipeline caused by the lack of I-Cache and improving the efficiency of the pipeline. However, when the shared I-Cache resources assigned to each hardware thread are insufficient, the I-Cache miss rate increases, and the missing requests...

AI Technical Summary

Problems solved by technology

However, when the shared I-Cache resources assigned to each hardware thread are insufficient, the I-Cache miss rate increases, and the missing requests sent from the I-Cache to the next-level Cache will occur frequently, and instructions will be retrieved from the next-level Cache. When backfilling, when the thread data increases, the Cache line where the filled instruction is located will be immediately filled into the missing I-Cache and will not be used immediately, and the replaced Cache line may be used again

[0004] In addition, when adjusting the scheduling strategy of Thread (thread) according to the Cache hit situation, it will try to ensure that the thread with a high hit rate of memory access instructions in the Cache is prioritized for a period of time, but for the shared I allocated to each hardware thread -The problem of insufficient Cache resources has not been improved

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