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Non-volatile memory device

A non-volatile storage and storage layer technology, applied in information storage, static memory, digital memory information, etc., can solve the problems of affecting the storage state and reducing the reliability of storage devices, and achieve the effect of suppressing crosstalk

Active Publication Date: 2015-01-14
키오시아가부시키가이샤
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] In this case, when one of the two memory cells facing each other across the bit line is selected, its operation may affect the storage state of the other memory cell.
Such a phenomenon becomes a cause of a malfunction called "crosstalk" and reduces the reliability of the memory device.

Method used

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Examples

Experimental program
Comparison scheme
Effect test

no. 1 Embodiment

[0022] The nonvolatile memory device 100 of the first embodiment includes a memory cell array 1 having a three-dimensional structure. The memory cell array 1 includes, for example, a plurality of variable resistance memory cells MC.

[0023] Below, refer to Figure 1 ~ Figure 4 , the nonvolatile memory device 100 of the first embodiment will be described.

[0024] figure 1 It is an example of a perspective view schematically showing the memory cell array 1 . The memory cell array 1 includes: a first wiring extending in a first direction; a second wiring extending in a second direction perpendicular to the first direction and electrically connected to the first wiring; A plurality of third wirings respectively extending in third directions perpendicular to each other.

[0025] In this example, the first direction is the X direction, the second direction is the Z direction, and the third direction is the Y direction. The extending directions of the respective wirings are pe...

no. 2 Embodiment

[0091] Figure 14 It is an example of a cross-sectional view schematically showing the memory cell array 5 of the second embodiment.

[0092] Such as Figure 14 , in the memory cell array 5, the local bit line 20 has a gap 47 between the first portion 21 connected to the first memory layer 40a and the second portion 23 connected to the second memory layer 40b. For example, Figure 10A In the process shown, the deposition is stopped before the conductive layers 67 deposited on both side walls of the slit 65 are connected in the X direction. Therefore, a gap can remain between the first part 21 and the second part 23 .

[0093] The gap 47 extends in the Z direction in the local bit line 20 . The gap 47 prevents carriers flowing from one of the word lines 30a and 30b to the local bit line 20 through the storage layer 40 from moving to the other of the word lines 30a and 30b. Accordingly, crosstalk between memory cells facing each other across the local bit line 20 can be sup...

no. 3 Embodiment

[0098] Figure 15 It is an example of a cross-sectional view schematically showing the memory cell array 6 of the nonvolatile memory device 200 of the third embodiment.

[0099] The nonvolatile memory device 200 has a so-called vertical cross-point structure, and the local bit line 20 is directly connected to the global bit line 10 . Between the local bit line 20 and the word line 30 a rectifying element, such as a diode, is arranged.

[0100] Such as Figure 15 , in the memory cell array 6 , the global bit line 10 is directly connected to the local bit line 20 . A plurality of word lines 30 are arranged side by side on both sides of the local bit line 20 . In addition, in this example, the word line 30 arranged between adjacent local bit lines 20 in the X direction faces any one of the local bit lines 20 via the memory layer 40 . The memory layer 40 includes a variable resistance layer 42 provided on the side of the word line 30 and a rectifying layer 71 connected to the ...

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PUM

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Abstract

According to an embodiment, a non-volatile memory device includes a first wiring extending in a first direction, a second wiring extending in a second direction orthogonal to the first direction. The device includes third wirings, and a first and a second memory. The third wirings extend in a third direction crossing the first direction and orthogonal to the second direction, and aligned in the second direction on both sides of the second wiring. The first memory is provided between one of third wiring pair and the second wiring, the pair of third wirings facing each other across the second wiring. The second memory is provided between another one of the third wiring pair and the second wiring. The second wiring has a block portion between a first portion in contact with the first memory and a second portion in contact with the second memory.

Description

[0001] related application [0002] This application takes U.S. Provisional Patent Application No. 61 / 844, No. 234 (filing date: July 9, 2013) as the basic application, and enjoys the right of priority. This application incorporates the entire content of the basic application by referring to this basic application. technical field [0003] Embodiments relate to non-volatile memory devices. Background technique [0004] In order to realize a next-generation nonvolatile memory device, the development of a memory cell array having a three-dimensional structure is further advanced. For example, there is a structure in which a plurality of bit lines extending in a direction perpendicular to a base semiconductor substrate are provided, and a plurality of memory cells are arranged along each extending direction. In the memory cell array having such a structure, a cell structure is adopted in which a memory layer is provided on the sidewall of the bit line. In order to increase t...

Claims

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Application Information

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IPC IPC(8): H01L27/24G11C13/00
CPCH01L45/12H10B63/34H10B63/845H10N70/245H10N70/823H10N70/20H10N70/883H10N70/023H10N70/8833H10N70/011H10B63/30H10N70/25H10N70/063H10N70/881
Inventor 菅野裕士峰村洋一冢本隆之大川隆圣吉田敦田端英之
Owner 키오시아가부시키가이샤
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