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Increasing the efficiency of memory resources in a processor

A memory and resource technology, applied in memory systems, instruments, program save/restore, etc., can solve problems such as short delay

Inactive Publication Date: 2015-03-18
MIPS TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The cache is smaller than main memory 108 which can be implemented in DRAM, but the latency involved in accessing the cache is much shorter compared to main memory

Method used

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  • Increasing the efficiency of memory resources in a processor
  • Increasing the efficiency of memory resources in a processor
  • Increasing the efficiency of memory resources in a processor

Examples

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Embodiment Construction

[0025] Embodiments of the invention are described below, by way of example only. These examples represent the best mode of carrying out the invention, which is presently known to the applicant, but they are not the only way in which this can be carried out. The description sets forth the function of the example and a sequence of steps for making and operating the example. However, the same or equivalent functions and sequences may be implemented by different examples.

[0026] As noted above, processors that can execute DSP instructions typically include additional register resources dedicated to use by those DSP instructions. figure 2 A schematic diagram of an exemplary multithreaded processor 200 including two threads 202, 204 is shown. In addition to local registers 206 and global registers 208, there are a small number of dedicated DSP registers 210 and many more indirect access DSP registers 211 (which may be referred to as DSP indirect registers). These DSP indirect ...

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Abstract

Methods of increasing the efficiency of memory resources within a processor are described. In an embodiment, instead of including dedicated DSP indirect register resource for storing data associated with DSP instructions, this data is stored in an allocated and locked region within the cache. The state of any cache lines which are used to store DSP data is then set to prevent the data from being written to memory. The size of the allocated region within the cache may vary according to the amount of DSP data that needs to be stored and when no DSP instructions are being run, no cache resources are allocated for storage of DSP data.

Description

Background technique [0001] A processor typically includes a number of registers, and where the processor is a multi-threaded processor, the registers may be shared between threads (global registers) or dedicated to a particular thread (local registers). Where the processor executes DSP (Digital Signal Processing) instructions, the processor includes additional registers used exclusively by the DSP instructions. [0002] The processor's registers 100 form part of a memory hierarchy 10 arranged to reduce the latency associated with accessing main memory 108, as figure 1 shown. The memory hierarchy consists of one or more caches, and typically there are two levels of on-chip cache L1102 and L2 104 typically implemented using SRAM (Static Random Access Memory) and one level of off-chip cache L3106. L1 cache 102 is closer to the processor than L2 cache 104 . The cache is smaller than main memory 108 which can be implemented in DRAM, but the latencies involved in accessing the c...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/08G06F12/084G06F12/0842G06F12/0846G06F12/0855G06F12/0875G06F12/126
CPCG06F12/0875G06F2212/452G06F9/461G06F12/084G06F12/126G06F12/0842G06F12/0848G06F12/0855
Inventor J·梅雷迪思R·G·伊舍伍德H·杰克逊
Owner MIPS TECH INC