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Serial communication protocol controller, byte splitting circuit and 8b10b encoder

A serial communication protocol, 8b10b technology, applied in the field of microelectronics, can solve the problems that the highest operating frequency of the circuit is difficult to reach 500MHz, the chip area and power consumption are increased, and the highest frequency of the encoder is high. The effect of saving and reducing design difficulty

Active Publication Date: 2015-03-25
SHANDONG SINOCHIP SEMICON
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0007] There are two commonly used encoding circuit design methods: one is to store the corresponding rules of 256 data codes and 12 function codes in memory, and the encoding process is divided into two parts: mapping and polarity selection. This method will increase the size of the chip. The area and power consumption are limited by the speed of the lookup table and the process

Method used

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  • Serial communication protocol controller, byte splitting circuit and 8b10b encoder
  • Serial communication protocol controller, byte splitting circuit and 8b10b encoder
  • Serial communication protocol controller, byte splitting circuit and 8b10b encoder

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Embodiment 1

[0028] Such as figure 2 As shown, a serial communication protocol controller provided by the present invention includes a byte splitting circuit and an 8b10b encoder, and the byte splitting circuit completes different clock frequencies and different bit widths between the system bus data and the 8b / 10b encoder The matching of the data, the 8b / 10b encoder encodes and sends to the parallel-serial conversion circuit. This embodiment introduces the most commonly used SATA high-speed serial communication protocol, but is not limited to the SATA high-speed serial communication protocol.

[0029] Such as figure 2 , 3 As shown, the byte splitting circuit includes a FIFO with a depth of 4 and a bit width of 32, a controller and a register, and adjusts the 32-bit input bus data at a clock frequency of 150MHz to output data at 4 beats and 8 bits at a clock frequency of 600MHz, and transmits to 8b / 10b encoders. The byte splitting circuit extracts the bus data byte 0, byte 1, byte 2, ...

Embodiment 2

[0033] The present invention also provides the byte splitting circuit used for the serial communication protocol controller in the first embodiment.

Embodiment 3

[0035] The present invention also provides the 8b / 10b encoder used for the serial communication protocol controller in the first embodiment.

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Abstract

The invention discloses a serial communication protocol controller which comprises a byte splitting circuit and an 8b10b encoder. The byte splitting circuit receives bus data and transmits the bus data to the 8b10b encoder. Matching of different clock frequencies and different bit widths between the bus data and the 8b10b encoder is completed. The byte splitting circuit comprises FIFO, a controller and a register. The byte splitting circuit extracts 32 bit bus date bytes 0, 1, 2 and 3 to form source data words 1 and bytes 5, 6 and 7 to form source data words 2, 4-beat-8-bit output data are obtained and then are written into the FIFO in sequence, then the data are read into the register under the effect of the controller, and meanwhile the data are transmitted to the encoder input end according to the order from low bytes to high bytes. The invention further provides the byte splitting circuit and the 8b10b encoder used in the serial communication protocol controller. Matching of high-speed serial communication protocol emitting end data bandwidth is effectively achieved.

Description

technical field [0001] The present invention relates to the technical field of microelectronics, in particular to a high-speed serial communication protocol controller circuit, in particular to a byte splitting circuit and an 8b10b encoder. Background technique [0002] In the traditional parallel data transmission mode, the data transmission mode generally adopts a special data bus and a clock line for synchronous transmission. The bandwidth limitation of the traditional parallel bus can no longer meet the astonishing demands of the development of the hardware subsystem speed and the increasing data throughput, which is mainly manifested in the following two aspects: As the bus frequency rises, it will affect the connection to the bus at the same frequency. Therefore, even if the bus clock frequency is increased, the bus bandwidth cannot be significantly improved; although the bandwidth can be increased by increasing the number of parallel channels, the synchronous transmis...

Claims

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Application Information

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IPC IPC(8): H03M7/02G06F13/42
Inventor 刘奇浩孙晓宁刘大铕王运哲赵阳
Owner SHANDONG SINOCHIP SEMICON
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