Data prefetching method based on location awareness in on-chip cache network

Abstract

The invention discloses a data prefetching method based on location awareness in an on-chip cache network. The data prefetching method based on location awareness in the on-chip cache network comprises the following steps: 1) after a processor is started, recording cache block information of data fetched into the on-chip cache network on the processor in the on-chip cache network by using a data location vector table; 2) when a processor core executes a prefetching instruction in a program, skipping to execute step 3); 3) searching the cache block information of target data of the prefetching instruction in the on-chip cache network from the data location vector table, prefetching the target data, then storing the target data in a cache block designated by the prefetching instruction, and updating the cache block information of the target data in the on-chip cache network. The data prefetching method based on location awareness in the on-chip cache network can realize prefetching of data in the on-chip cache network on the many-core processor, and has the advantages of simple realization principle, high prefetching accuracy and high flexibility.

Description

Technical field [0001] The invention relates to the technical field of storage access for many-core processors, and in particular to a data prefetching method based on location awareness in an on-chip Cache network. Background technique [0002] The memory wall means that the time for the processor to access the memory to obtain instructions and data is much higher than the time for executing instructions in the processor, which is one of the main factors restricting the performance of the processor. At present, with the rapid development of on-chip multi-core and even many-core architectures, the memory wall problem of many-core processors has become more prominent. In order to alleviate the storage wall problem, multi-level Cache (cache) is usually designed on the processor chip. Each processor core of the many-core processor is usually designed to match the local Cache, and the on-chip Cache of many processor cores constitutes the on-chip Cache network. During the working pr...

AI Technical Summary

Problems solved by technology

Although the software prefetching method improves the flexibility and adaptability of prefetching, it requires programmers or compilers to insert prefetching operations, which increases the difficulty of programming or increases the complexity of compiler implementation; in addition, software prefetching The effect of also greatly depends on the accuracy of software prefetching

[0006] Compared with a specific processor core, the data read time of many Cache blocks in the on-chip Cache network is very different. It is necessary to place the prefetched data in the Cache block as close as possible to the processor core. Therefore, for On-chip Cache network of many-core processors, software prefetching is very complicated, not only the timing of prefetching but also the location of prefetched data storage in the on-chip Cache network must be considered

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