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Video decoding processing apparatus and operating method thereof

A technology of video processing and processing devices, which is applied in the direction of digital video signal modification, electrical components, image communication, etc., and can solve problems such as increasing screen size

Inactive Publication Date: 2015-04-15
RENESAS ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0017] On the other hand, with respect to digital HDTV (High Definition Television) broadcast receivers, digital video cameras capable of shooting or capturing HDTV signals, and the like, the screen size of systems that process moving picture codes increases

Method used

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  • Video decoding processing apparatus and operating method thereof
  • Video decoding processing apparatus and operating method thereof
  • Video decoding processing apparatus and operating method thereof

Examples

Experimental program
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Embodiment 1

[0113] (Structure of video decoding processing device)

[0114] figure 1 is a diagram showing the configuration of the video decoding processing device 1 according to Embodiment 1.

[0115] according to figure 1 The video decoding processing device 1 of the illustrated embodiment has an analysis unit 10, a plurality of video processing units 20, 21, 22, 23, ... and 27, a video construction unit 30, and a plurality of inter-unit signal buses 41, 42, 43, …, and 47.

[0116] >

[0117] The parsing unit 10 performs parsing (syntax interpretation) of the bit stream BS encoded in the H.265 / HEVC standard and functions as an entropy decoding unit that performs variable-length decoding.

[0118] figure 1 Each of the shown video encoding processing devices performs parallel encoding processing according to its own encoding strategy, thereby generating an encoded bit stream BS conforming to the H.265 / HEVC standard.

[0119] Thus, according to figure 1 The analysis unit 10 of the vid...

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Abstract

Disclosed is a video decoding processing apparatus which can reduce overhead for the start of parallel decoding processing. The video decoding processing apparatus includes a parsing unit, and first and second video processing units. A coding bit stream including information of largest coding units each having at least a prescribed pixel size is supplied to an input terminal of the parsing unit. The parsing unit performs parsing of the syntax of the coding bit stream to thereby generate parallel-processable first and second intermediate streams from the largest coding unit. The first and second video processing units parallel-process the first and second intermediate streams generated from the parsing unit.

Description

[0001] Cross References to Related Applications [0002] The disclosure of Japanese Patent Application No. 2013-207145 filed on October 2, 2013 including specification, drawings and abstract is incorporated herein by reference in its entirety. technical field [0003] The present invention relates to a video decoding processing device and an operating method thereof, and more particularly, to a technique effective in reducing the overhead of starting parallel decoding processing. Background technique [0004] As is well known, common compression systems for moving pictures based on the standard MPEG-2 standardized by the international standard ISO / IEC 13818-2 are based on the principle of reducing video storage capacity and required bandwidth by reducing redundant information from a video stream. Incidentally, MPEG is an acronym for Moving Picture Experts Group. [0005] Since the MPEG-2 standard only defines the syntax of the bit stream (the rules for compressing and encod...

Claims

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Application Information

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IPC IPC(8): H04N19/61H04N19/176H04N19/124H04N19/96
CPCH04N19/44H04N19/50H04N19/70H04N19/436H04N19/61
Inventor 柴山哲也望月诚二岩田宪一木村基
Owner RENESAS ELECTRONICS CORP
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