Trench power MOS device and manufacturing method thereof

Abstract

The invention relates to a deep-groove power MOS (metal oxide semiconductor) device with ultrahigh cellular density and a manufacturing method of the deep-groove power MOS device. Cells in a cellular area adopt groove structures, gate oxidation layers are grown on the section of the power MOS device and the inner wall and the bottom of cellular grooves, and conductive polycrystalline silicon is deposited in the cellular grooves. Thermal oxidation layers are arranged in notches of the cellular grooves, insulation medium layers are deposited on the thermal oxidation layers, and the insulation medium layers and the thermal oxidation layer are distributed in the notches of the cellular grooves only. On the section of the power MOS device, source contact holes extend into a second conductive type trap layer downwards from a first conductive type source electrode and are filled with source metal, and the source metal contacts with the first conductive type source area and the second conductive type trap layer. The deep-groove power MOS device is compact in structure, groove resistance of the MOS device can be greatly reduced, and characteristic conduction resistance of the integral device is reduced.

Description

technical field [0001] The invention relates to a power MOS device and a manufacturing method thereof, in particular to a trench power MOS device and a manufacturing method thereof, belonging to the technical field of power semiconductor devices. Background technique [0002] Trench power MOS devices have the characteristics of high integration, low on-resistance, fast switching speed, and low switching loss, and are widely used in various power management and switching conversions. With the development of industry, global warming has caused the climate environment to become more and more severe, and countries have begun to pay more and more attention to energy conservation, carbon reduction and sustainable development. Therefore, the requirements for power consumption and conversion efficiency of power MOS devices are getting higher and higher. When the application frequency is not high, the power consumption is mainly determined by the conduction loss, which is mainly affe...

AI Technical Summary

Problems solved by technology

At present, the domestic mass production process can expose and maintain the minimum cell trench line width of about 0.25 μm after etching. After the final etching and fabrication of sacrificial oxide layer and insulating gate oxide layer, the trench line width is about 0.4 μm. The line width of the minimum cellular contact hole that can be exposed in domestic mass production and maintain a good shape after etching is about 0.25 μm, and the alignment accuracy of a 248nm DUV lithography machine is about 60nm. The pitch of the cell trenches of the insulating gate oxide layer is at least 0.09 μm, so the minimum achievable pitch of the existing technology is about 0.83 μm, which is difficult to further reduce

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