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Sonos device manufacturing process method

A manufacturing process and device technology, applied in the field of SONOS device manufacturing process, can solve problems such as being susceptible to interference, selection tubes and storage tubes do not share source and drain regions, etc., to reduce area, realize self-aligned etching, and reduce selection. tube effect

Active Publication Date: 2020-08-11
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
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  • Application Information

AI Technical Summary

Problems solved by technology

In 2-T SONOS applications, since the source and drain terminals of the SONOS storage tube are directly connected to a fixed voltage during operation, they are susceptible to interference
[0004] Although the above-mentioned SONOS storage tube fully isolated device structure is composed of three devices, there is no shared source and drain region between the selection tube and the storage tube.

Method used

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Embodiment Construction

[0024] Described self-aligned SONOS device manufacture process method is in the following embodiment, implementation process is as follows:

[0025] Step 1, see Figure 4 A first oxide layer 17 is formed on the upper end of the P-type substrate 1, and the oxide layer 17 is used to finally form the gate oxide layer 8 of the transistor in the logic region and the gate oxide layer 2 of the selection transistor. A first polysilicon layer 18 and a first silicon nitride layer 22 are sequentially deposited on the first oxide layer 17, and the first polysilicon layer 18 is used to form the select transistor polysilicon gate 5 and the logic region transistor polysilicon Grid 23. The first silicon nitride layer 22 is used as a reserved layer of the CMP (chemical mechanical polishing) stop layer, and its deposited thickness is

[0026] Step 2, see Figure 5 , the photolithography is opened, the first silicon nitride layer 22 is etched, and the first polysilicon layer 18 is implanted...

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Abstract

The invention discloses a self-aligned SONOS device manufacturing process method. The selection transistor polysilicon gate adopts self-alignment etching, so that the size of the selection transistor is not limited by photolithography, which is beneficial to shrinking the selection transistor; the source-drain contact hole of the storage unit The use of self-aligned etching is conducive to reducing the area of ​​the memory unit. The invention can reduce the area of ​​the storage unit.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuits, in particular to a manufacturing process method of a SONOS (Semiconductor-Oxide-Nitride-Oxide-Semiconductor flash memory) device. Background technique [0002] SONOS technology with low operating voltage and better CMOS process compatibility is widely used in various embedded electronic products, such as financial IC cards, automotive electronics and other applications. 2-T SONOS (2transistors two transistors store one bit of data) technology has been favored by many low-power applications due to its low power consumption. In 2-T SONOS applications, since the source and drain terminals of the SONOS storage tube are directly connected to a fixed voltage during operation, they are susceptible to interference. The use of SONOS memory tube fully isolated device structure can better suppress various interferences and improve device performance. [0003] The structure of SONOS storage...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/1157H10B43/35
CPCH10B43/35
Inventor 许昭昭
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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