A plc program scheduler ip core based on amba bus

Abstract

The invention discloses a PLC program scheduler IP core based on an AMBA bus. The PLC program scheduler IP core includes an AHB interface module, a cycle task scheduling module, a timed task scheduling module and an interrupt task scheduling module, wherein the AHB interface includes a plurality of registers, a controller configures task information for the register and monitors task states of the register by the AMBA bus, the task information includes a program section number and a data section number, and the PLC program scheduler IP core based on the AMBA bus provides the program section number and the data section number to an executer for executing corresponding tasks; the cycle task scheduling module is connected with the AHB interface module for scheduling cycle tasks; the timed task scheduling module is connected with the AHB interface module and the cycle task scheduling module for scheduling timed tasks and pending the cycle task scheduling module; the interrupt task scheduling module is connected with the AHB interface module, the cycle task scheduling module and the timed task scheduling module for scheduling interrupt tasks, and pending the cycle task scheduling module and the timed task scheduling module.

Description

technical field [0001] The invention relates to the field of programmable logic controllers, in particular to a PLC program scheduler IP core based on AMBA bus. Background technique [0002] With the development of automatic control technology, programmable logic controller (PLC) has been more and more used in various industries, and the standardization level is getting higher and higher. At present, a series of international standards (IEC61131) such as the typical structure of PLC controllers, programming languages, communications, and user guidelines have been formed. Among them, the programming language standard (IEC61131-3) is the most widely used, and all programmable controllers need to support the five languages ​​supported by the standard, including IL, ST, LD, FBD and SFC. [0003] In the PLC controller structure with the microprogram controller (MCU) as the processing core, both the task scheduling of the PLC and the execution of specific tasks are based on the M...

AI Technical Summary

Problems solved by technology

[0003] In the PLC controller structure with the microprogram controller (MCU) as the processing core, both the task scheduling of the PLC and the execution of specific tasks are based on the MCU and the embedded operating system. PLC task scheduling and execution need Occupies a lot of MCU work, and MCU usually needs to complete other important tasks (such as communication, display), the execution and response speed of PLC tasks are therefore affected by other tasks of MCU, it is difficult to guarantee its real-time and reliability

In order to limitedly improve the PLC task processing performance, the current PLC system is working towards a more advanced and faster MCU, but the target versatility of the MCU is bound to cause idleness and waste of many functional parts of these advanced MCUs

Moreover, every time the MCU is upgraded, the PLC operating system based on the MCU needs to be redesigned. The upgrade cost is high and the performance improvement is limited.

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