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Method for manufacturing wafer level package

A technology of wafer-level packaging and manufacturing methods, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., to achieve the effect of reducing risks

Inactive Publication Date: 2015-05-13
NANTONG FUJITSU MICROELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

At the same time of flip-chip and stacking, the packaging thickness is also required to be as thin as possible, so to a certain extent, the chip packaging is required to be as thin as possible, resulting in the risk of processing

Method used

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  • Method for manufacturing wafer level package
  • Method for manufacturing wafer level package
  • Method for manufacturing wafer level package

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Embodiment Construction

[0013] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of embodiments of the present invention, but not all embodiments. Elements and features described in one drawing or one embodiment of the present invention may be combined with elements and features shown in one or more other drawings or embodiments. It should be noted that representation and description of components and processes that are not related to the present invention and known to those of ordinary skill in the art are omitted from the drawings and descriptions for the purpose of clarity. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the ar...

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Abstract

The invention relates to a method for manufacturing a wafer level package; the method comprises the steps: forming a first photoresist on a first chip, forming a plurality of first opening parts on the first photoresist and exposing the functional side of the first chip; forming an under-bump metal layer on the functional side exposed at the first opening parts and then removing the first photoresist; connecting functional bumps of a second chip and the under-bump metal layer; forming a filling layer between the first chip and the second chip; forming a connecting layer on the first chip and enabling the top surface of the connecting layer to be higher than the top surface of the second chip; and planting solder balls on the top surface of the connecting layer. The first chip and the second chip are arranged face to face; the connecting layer is formed on the first chip; in the subsequent inverting and packaging process, the formed package structure can be inverted and packaged by utilizing a height difference between the connecting layer on the first chip and the second chip; the package structure is not damaged, that is, the second chip is not damaged during inversion and packaging; and the risk during processing is reduced.

Description

technical field [0001] The invention relates to a semiconductor manufacturing method, in particular to a wafer-level packaging manufacturing method. Background technique [0002] With more and more chip functions, the requirements for packaging are getting higher and higher, and flip-chip and stacking have become a trend. At the same time of flip-chip and stacking, the thickness of the package is also required to be as thin as possible. This requires the chip package to be as thin as possible to a certain extent, resulting in risks in the processing process. Contents of the invention [0003] A brief overview of the invention is given below in order to provide a basic understanding of some aspects of the invention. It should be understood that this summary is not an exhaustive overview of the invention. It is not intended to identify key or critical parts of the invention nor to delineate the scope of the invention. Its purpose is merely to present some concepts in a si...

Claims

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Application Information

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IPC IPC(8): H01L21/56H01L21/60
CPCH01L24/81H01L21/563H01L2224/16225H01L2224/32225H01L2224/73204H01L2924/00H01L2224/32145H01L2224/16145
Inventor 丁万春
Owner NANTONG FUJITSU MICROELECTRONICS
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