ROM read data internal clock pulse generation circuit and method

Abstract

The invention discloses an ROM read data internal clock pulse generation circuit. The ROM read data internal clock pulse generation circuit comprises a logic control circuit, a reference bit charging / discharging control circuit, a sensitive amplification circuit and a reference bit, wherein a load of the reference bit is a changeable load; after the changeable load is written into an ROM circuit according to an ROM data code, a maximum bit load in the ROM circuit is adjusted; the reference bit charging / discharging control circuit is used for charging and discharging the reference bit to obtain charging and discharging time of the reference bit; and an internal clock pulse is generated by the sensitive amplification circuit and the logic control circuit, and the pulse width of the internal clock pulse guarantees that accurate reading is realized by sufficient time margin when data on the bit corresponding to the maximum bit load is read. The invention further discloses an ROM read data internal clock pulse generation method. The ROM power consumption and reading time can be reduced.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a ROM read data internal clock pulse generation circuit; the invention also relates to a ROM read data internal clock pulse generation method. Background technique [0002] A read-only memory (Read-Only Memory, ROM) is a memory that can only read data. In the wafer manufacturing process, the ROM data code (Code) provided by the customer is usually manufactured in the ROM circuit with a special mask (Mask). The ROM Code here refers to the data that the customer needs to write into the ROM circuit. Code Once written, it cannot be changed. [0003] For ROM, general users are more concerned about the following parameters: 1) ROM area; 2) ROM power consumption; 3) ROM reading speed. [0004] When the same ROM is written into different ROM Codes, the load on the ROM bit line (Bit Line, BL) will also be different, and the load on the bit line is the writte...

AI Technical Summary

Problems solved by technology

However, in actual use, the Rom Code of many users does not allow the bit line to be fully loaded.

In this case, the too wide internal clock pulse will have a large time margin after successfully reading the data, and these time margins will bring the following two disadvantages: 1) ROM power consumption rises; 2) ROM reading speed slowing down

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