Multi-Master Arbitration Method in Dynamically Reconfigurable High Speed Serial Bus
A technology of high-speed serial bus and arbitration method, which is applied in the field of multi-master arbitration, can solve the problems of unsatisfactory UM-BUS bus real-time performance, reliability, poor bandwidth utilization rate, and low arbitration efficiency, so as to reduce the waste of communication resources, The effect of improving reliability and improving real-time performance
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[0026] Based on above-mentioned UM-BUS main line working principle, a kind of specific implementation of multi-master arbitration method of the present invention is as follows:
[0027] For the convenience of description, it is assumed that the UM-BUS bus supports 8 master nodes, the node number is defined as 0~7, the bus single-channel communication rate is 200Mbps, the working clock of the bus MAC sublayer is 100MHz, and the maximum transmission time of bus signals between nodes is 260ns. A time slice timer of an arbitration time slot timer and an arbitration time slot counter is set in the UM-BUS bus node controller to generate the timing and counting of the required arbitration time slots. In order to ensure that in the worst case, each node of the bus can detect the occupancy of the bus by the master node within an arbitration time slot, the timing length of the arbitration time slot is set to 500ns in this embodiment. The value range of the arbitration slot counter is 0...
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