Optimal read data circuit in data storage flash memory
A technology for data storage and data reading, applied in the field of memory read and write operations, can solve problems such as large parasitic capacitance, erroneous data readout, and difficulty in flipping a chip latch, and achieve the effect of avoiding difficulty in flipping and ensuring accuracy.
Active Publication Date: 2019-02-22
GIGADEVICE SEMICON (BEIJING) INC
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Problems solved by technology
In data-storage flash memory, due to the increase in storage capacity, the parasitic capacitance of some nodes is very large, which may easily lead to difficulties in flipping the internal latches of the chip, resulting in wrong data readout, affecting the normal use of data-storage flash memory
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Embodiment 2
[0061] The working process of the optimized data reading circuit in a data storage type flash memory provided by the embodiment of the present invention is as follows:
[0062] 1. The data buffer 170 sends electrical signals with voltage values bl and bl_b to the chip optimized data read circuit. Wherein, bl and bl_b are electrical signals with equal voltage values but different positive and negative values, which are respectively applied to the first input terminal and the second input terminal of the voltage regulation module 110; the drain of the first transistor 150 and the source of the second transistor 160; The drain of the fourteenth transistor and the drain of the fifteenth transistor in the auxiliary module 140 . It should be noted that when bl and bl_b are output from the data latch PDL to the above module, the voltage value of one of bl and bl_b will drop slightly due to the data latch itself.
[0063] 2. When bl and bl_b are loaded to the drain of the first t...
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The present invention provides an optimal data reading circuit in a data storage type flash memory, which comprises a voltage regulating module, a latch module, a control signal module, a first transistor and a second transistor. The input end of the voltage regulating module is connected with the output end of a data cache; the control end of the voltage regulating module is connected with the output end of a voltage regulating circuit; the input end of the latch module is respectively connected with the first transistor and the second transistor; the input end of the control signal module is respectively connected with the output end of the latch module and the output end of the control signal module is connected with a data path; and a drain electrode of the first transistor is connected with the first output end of the data cache, a source electrode of the second transistor is connected with the second output end of the data cache, and grid electrodes of the first transistor and the second transistor are connected and are connected with the first input end of an external control circuit. According to the present invention, by adding two transistors between the external data cache and the latch module, influence of stray capacitances caused by a plurality of data caches on normal working of a latch is eliminated.
Description
technical field [0001] The invention relates to the technical field of memory reading and writing operations, in particular to an optimized data reading circuit in a data storage type flash memory. Background technique [0002] With the continuous development of electronic products, chip technology is also undergoing tremendous changes. As a kind of flash memory, data storage flash memory provides a cheap and effective solution for the realization of solid-state large-capacity memory due to its internal nonlinear macrocell mode. Data storage flash memory has the advantages of large capacity and fast rewriting speed, and is suitable for storing large amounts of data, so it has been more and more widely used in the industry. For example, embedded products include digital cameras, MP3 walkman memory cards, Small and exquisite U disk, etc. [0003] However, data storage flash memory also has certain deficiencies in its application field. In data-storage flash memory, due to t...
Claims
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IPC IPC(8): G11C16/26G11C16/10
Inventor 苏志强丁冲谢瑞杰陈立刚
Owner GIGADEVICE SEMICON (BEIJING) INC