VDMOS device and manufacturing method thereof

A device and control gate technology, which is applied in the field of VDMOS devices and its manufacturing, can solve the problems of reduced withstand voltage, increased on-resistance, and increased process complexity, and achieve the effect of reducing Miller capacitance and on-resistance

Inactive Publication Date: 2015-10-21
UNIV OF ELECTRONIC SCI & TECH OF CHINA
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Problems solved by technology

However, this structure requires two polysilicon gates in the process, which increases the complexity of the process.
[0006] In addition, there is a common problem in the several methods of reducing Miller capacitance mentioned in the above traditional methods: since the JFET area of ​​the device is no longer covered by the gate electrode, when the device is conducting forward, it will not be in the same way as the conventional VDMOS. The accumulation layer with high carrier concentration is formed on the

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  • VDMOS device and manufacturing method thereof
  • VDMOS device and manufacturing method thereof
  • VDMOS device and manufacturing method thereof

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Embodiment Construction

[0038] Below in conjunction with accompanying drawing, describe technical scheme of the present invention in detail:

[0039] The present invention proposes a VDMOS device, such as Figure 5 As shown, it includes a semiconductor substrate 9 of the first conductivity type and a semiconductor epitaxial layer 8 of the first conductivity type arranged on the upper surface of the semiconductor substrate 9 of the first conductivity type. The bottom and the drain electrode of the semiconductor substrate 9 of the first conductivity type The metal electrode 10 is connected; the two ends of the upper layer of the first conductivity type semiconductor epitaxial layer 8 have a second conductivity type semiconductor body region 6, and the second conductivity type semiconductor body region 6 has a first conductivity type semiconductor source region 5 and a second conductivity type semiconductor body region. The second conductivity type semiconductor body contact region 7; the first conductivi...

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Abstract

The invention relates to the technical field of semiconductor devices, and specifically relates to a VDMOS device with a relatively-low Miller capacitor and a manufacturing method of the VDMC device. According to the technical scheme of the invention, a groove filled with oxide is arranged in an epitaxial layer below grids, and the grids are controlled to be above a thick oxide layer medium, so that a semiconductor surface high electric field generated at the tail end of a control grid is reduced, and the reduction of a device voltage resistance level is prevented. The VDMOS device has the advantage that the power VDMOS new structure with the relatively-low Miller capacitor can adopt a higher JFET concentration, so that the conductive resistance of the device is effectively reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductor devices, in particular to a VDMOS device with lower Miller capacitance and a manufacturing method thereof. Background technique [0002] Power VDMOS has higher switching speed and better frequency characteristics than bipolar power devices, and has been widely used in the field of high-frequency power electronics technology, among which it is one of its important uses as a switching device in a switching power supply. As a switching device, VDMOS improves the operating frequency of the switching power supply and effectively reduces the volume and weight of the power supply. But at high frequency, the power loss in the VDMOS switching conversion process will seriously affect the conversion efficiency of the switching power supply. Therefore, high-frequency high-efficiency power supplies require VDMOS to have short switching times. [0003] Miller capacitance Cgd is a gate-drain capacitance,...

Claims

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Application Information

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IPC IPC(8): H01L29/78H01L29/06H01L29/40H01L29/423H01L21/336
CPCH01L29/0603H01L29/407H01L29/42356H01L29/66712H01L29/7802
Inventor 任敏蔡果杨珏琳牛博郭绪阳曹晓峰李泽宏高巍张金平张波
Owner UNIV OF ELECTRONIC SCI & TECH OF CHINA
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