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Memory circuits and routing of conductive layers thereof

A memory circuit and conductive layer technology, applied in static memory, digital memory information, circuits, etc., can solve problems affecting RC time delay and other issues

Inactive Publication Date: 2015-11-25
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

High length / width ratio results in narrow wordline routing
A narrow wordline increases the resistance of the wordline, adversely affecting the RC time delay of signals passing through the wordline coupled to 128, 256 or more memory cells

Method used

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  • Memory circuits and routing of conductive layers thereof
  • Memory circuits and routing of conductive layers thereof
  • Memory circuits and routing of conductive layers thereof

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Embodiment Construction

[0048] In order to make the above-mentioned objects, features and advantages of the present invention more comprehensible, preferred embodiments will be described in detail below together with the accompanying drawings.

[0049]It can be appreciated that the following disclosure provides many different embodiments or examples for implementing different features. Specific example combinations and permutations are described below to simplify the present invention. Of course this is only an example and not a limitation. For example, when describing the form of a first feature on a second feature, it may include that the first feature is in direct contact with the second feature, and it may include that an additional feature is formed between the first feature and the second feature such that The first and second features may not be in direct contact. In addition, the present invention may repeat reference numerals and / or letters in various embodiments. These repetitions are fo...

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Abstract

A memory circuit memory circuit comprises at least one memory cell for storing a datum. The memory cell is coupled with a word line, a bit line, a bit line bar, a first voltage line, and a second voltage line. A first conductive layer comprising a first landing pad and a second landing pad is arranged at a first level. A second conductive layer is coupled to the first conductive layer and arranged at a second level different from the first level. The second conductive layer is routed to define the first voltage line and the second voltage line. A third conductive layer is coupled to the second conductive layer and arranged at a third level different from the first level and the second level. The third conductive layer is routed to define the word line.

Description

[0001] This application is a divisional application of the invention patent application entitled "Wiring of memory circuit and its conductive layer" with the priority date of January 15, 2010 and the application number 201010002963.7 filed on January 15, 2010. technical field [0002] The present invention relates to semiconductor circuits, and more particularly to the wiring of memory circuits and their conductive layers. Background technique [0003] Memory circuits have been implemented in various applications. Memory circuits may include dynamic random access memory (DRAM), static random access memory (SRAM), and non-volatile memory circuits. An SRAM circuit includes a plurality of memory cells (cells). For a 6-T static memory that provides an array of memory cells, each of the memory cells contains six transistors. The 6-TSRAM memory cell is coupled to a bit line BL, an inverted bit line BLB and a word line WL. Four of the six transistors form two sets of interleaved...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C11/412H01L27/02H10B10/00
CPCH01L23/50G11C11/412H01L27/0207H01L27/11H01L27/1104H01L2924/0002H10B10/00H10B10/12H01L2924/00G11C5/06G11C5/063G11C11/4097
Inventor 廖忠志
Owner TAIWAN SEMICON MFG CO LTD