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Chip packaging substrate, chip packaging structure and manufacturing method

A technology for chip packaging and substrate fabrication, which is applied in semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, semiconductor devices, etc. It can solve the problems of lengthy manufacturing process and increased cost of chip packaging substrates, and achieve a streamlined process and cost-saving solutions. Effect

Active Publication Date: 2015-11-25
LEADING INTERCONNECT SEMICON TECH SHENZHEN CO LTD +2
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Although the thickness of the manufactured chip package substrate can be reduced, the process of the chip package substrate is lengthy and the cost increases

Method used

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  • Chip packaging substrate, chip packaging structure and manufacturing method
  • Chip packaging substrate, chip packaging structure and manufacturing method
  • Chip packaging substrate, chip packaging structure and manufacturing method

Examples

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[0049] In other embodiments, the substrate 11 may only include the carrier board 111 , the first adhesive layer 112 , the second adhesive layer 113 , the first original copper layer 116 and the second original copper layer 117 . The first adhesive layer 112 is located between the carrier board 111 and the first original copper layer 116 . The second adhesive layer 113 is located between the carrier board 111 and the second original copper layer 117 . At this time, the first adhesive layer 112 and the second adhesive layer 113 are both thermoplastic adhesive layers. In the subsequent board removal, it is only necessary to heat to the melting point of the first adhesive layer and the second adhesive layer 113 to realize the board removal, so that the first original copper layer 116 is separated from the first adhesive layer 112 to obtain the first separation board 16, and separating the second original copper layer 117 from the second adhesive layer 113 to obtain a second separ...

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Abstract

The invention relates to a chip packaging substrate, which comprises a conductive circuit, conductive columns and packaging colloid, wherein the conductive circuit comprises a raw copper layer and an electroplated layer; the conductive columns are arranged in a mode of protruding from the raw copper layer towards the direction away from the electroplated layer; each conductive column comprises an electroplated portion and a solder portion; the electroplated portion is located between the raw copper layer and the solder portion; the packaging colloid is formed at the surfaces of the raw copper layer and the conductive columns; the packaging colloid covers the raw copper layer and wraps the conductive columns; and the conductive columns are exposed from the packaging colloid. The invention further relates to a chip packaging structure provided with the chip packaging substrate and a manufacturing method thereof.

Description

technical field [0001] The invention relates to a chip packaging substrate, a chip packaging structure and a manufacturing method. Background technique [0002] With the development of thinner and lighter electronic products, chip packaging substrates are also becoming thinner and thinner. In the prior art, when manufacturing a thin chip packaging substrate, an electrical carrier is usually provided in advance and an electroplating conductive layer is formed on the electrical carrier, and part of the electrical carrier and electroplating conductive layer are finally removed. Although the thickness of the manufactured chip packaging substrate can be reduced, the manufacturing process of the chip packaging substrate is lengthy and the cost increases. Contents of the invention [0003] In view of this, it is necessary to provide a chip packaging substrate, a chip packaging structure and a manufacturing method that overcome the above-mentioned problems. [0004] A chip packa...

Claims

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Application Information

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IPC IPC(8): H01L23/498H01L23/31H01L21/60H01L21/56
Inventor 苏威硕
Owner LEADING INTERCONNECT SEMICON TECH SHENZHEN CO LTD