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A Hybrid Interconnect Structure for Network-on-Chip, Its Network Node Coding Method and its Hybrid Routing Algorithm

A network node, network-on-chip technology, applied in data exchange networks, forward error control, digital transmission systems, etc. Throughput, increase the average transmission delay, reduce the effect of the average distance of the path

Active Publication Date: 2018-05-01
58TH RES INST OF CETC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The disadvantages of this structural design are: symmetry can easily cause congestion and hotspots in the central area, resulting in unbalanced network load distribution; its edge nodes are relatively closed, and long-distance multi-hop communication between remote nodes is likely to cause delays. In terms of network architecture, consideration must be given Average path distance, scalability, number of nodes, network diameter, etc. of the topology
[0006] In practical applications, the communication frequency between each node of the on-chip network is different, and the communication between local cores is often more frequent. The above-mentioned single topological structures cannot take this difference into consideration. Difficult to meet real needs

Method used

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  • A Hybrid Interconnect Structure for Network-on-Chip, Its Network Node Coding Method and its Hybrid Routing Algorithm
  • A Hybrid Interconnect Structure for Network-on-Chip, Its Network Node Coding Method and its Hybrid Routing Algorithm
  • A Hybrid Interconnect Structure for Network-on-Chip, Its Network Node Coding Method and its Hybrid Routing Algorithm

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Experimental program
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Effect test

Embodiment 1

[0065] When network node B communicates with network node C, network node B is the source node, and network node C is the target node, it is judged that network node B and network node C are both network nodes on the two-dimensional mesh structure, and they are the same two-dimensional mesh The network nodes on the network execute the XY routing algorithm. The XY coordinates of network node B are (110, 101), and the XY coordinates of network node C are (001, 110). According to the calculation method of offset, Xoffset can be obtained =011, Yoffset=101, converted to decimal Xoffset is +3, Yoffset is -1. So take three steps in the positive direction of the X axis, and then take one step in the negative direction of the Y axis, that is, from network node B to network node C.

Embodiment 2

[0067] The network node G communicates with the network node N, the network node G is the source node, and the network node N is the target node. If the network node G and the network node N are all nodes on the binary tree structure of the global network, the binary tree routing algorithm is directly executed. As follows, the network node G point binary tree code is 00_10_10_11, the network node N point binary tree code is 00_11_10_00, find that the bit segment that is not equal for the first time from left to right is L2, and then find the source node G that is not equal for the first time from right to left The bit segment of 00 is L, and m=i-j+1=4-2+1=3 is calculated, that is, the parent node needs to be searched up three times to reach the first forked node D. Then, starting from the network node D, starting from the L2 bit of the target node N, according to figure 2 Make a judgment, the L2 bit of the target node N is 11, route to the right child node M of the network no...

Embodiment 3

[0069] Network node B communicates with network node J. Network node B is the source node, and network node J is the target node. According to the node position judgment method, it can be known that network node B and network node J are located on different two-dimensional mesh networks, and the network node For the routing algorithm from B to network node G on the binary tree structure, network node B is first routed to network node Y. Referring to Embodiment 1, it can be seen that network node Y can be reached by walking along the forward direction of X once. Then the network node Y directly routes to the network node G, and then performs the routing from the network node G to the network node N, refer to the second embodiment. After routing from network node G to network node N, direct routing from network node N to corresponding network node Q is performed, and then the route from network node Q to network node J is executed. Referring to Embodiment 1, it can be seen that t...

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Abstract

The present invention relates to a hybrid interconnect structure for a network on chip. The hybrid interconnection structure includes a global network and multiple local networks, the global network is a binary tree structure composed of multiple network nodes, the local network is a two-dimensional Mesh structure composed of multiple network nodes, and the local network The central node is connected to network nodes on the global network. In the present invention, the global network adopts a binary tree structure and the local network adopts a two-dimensional Mesh structure, and a matching network node encoding method and a hybrid routing algorithm are designed, so that the data flow between the local and the global can be balanced, and the traffic between local nodes can be reduced. The average path distance reduces the network diameter, thereby improving the average transmission delay and network data throughput of the network, and at the same time effectively saving connection resources. On the basis of the same connection resources, more network nodes can be added.

Description

technical field [0001] The invention belongs to the technical field of on-chip network interconnection, and in particular relates to a hybrid interconnection structure for an on-chip network, its network node encoding method and its hybrid routing algorithm. Background technique [0002] With the rapid development of semiconductor process technology, microelectronics technology is rapidly changing from integrated circuit design to system chip design. However, with the continuous development of process technology, some problems related to the characteristics of SoC (system-on-chip) itself have emerged, and such problems are difficult to solve under the traditional SoC architecture. Based on this situation, the concept of network on chip NoC (network onchip) was proposed around 1999. Its core idea is that the computing unit and the communication architecture are separated from each other, and its communication part draws on the computer network technology and transplants it i...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L12/751H04L12/721H04L1/00H04L45/02
CPCH04L1/0076H04L45/02H04L45/12
Inventor 刘海鹏屈凌翔凌爱民赵宝功汤赛楠
Owner 58TH RES INST OF CETC