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SOI-MOSFET model and parameter extracting method thereof

A parameter extraction and model technology, which is applied in electrical digital data processing, special data processing applications, instruments, etc., can solve problems such as complex models, difficult parameter extraction, and SOI-MOSFET models that cannot accurately reflect the characteristics of devices and frequencies.

Active Publication Date: 2015-12-09
SHANGHAI ADVANCED RES INST CHINESE ACADEMY OF SCI
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a SOI-MOSFET model and its parameter extraction method, which is used to solve the problem that the SOI-MOSFET model in the prior art is too simple to accurately reflect the characteristics of the device and frequency or The problem that the model is too complex makes parameter extraction difficult

Method used

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  • SOI-MOSFET model and parameter extracting method thereof
  • SOI-MOSFET model and parameter extracting method thereof
  • SOI-MOSFET model and parameter extracting method thereof

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Embodiment 1

[0072] This embodiment provides a SOI-MOSFET model, such as figure 2 and image 3 As shown, the SOI-MOSFET model includes a first model and a second model;

[0073] The first model is a substrate parasitic model, in which the source and drain terminals are short-circuited to form a source-drain terminal. The substrate parasitic model can be regarded as a two-port varactor, with the gate terminal as the input and the source and drain terminals as the As an output, substrate parasitic parameters can be extracted using the first model.

[0074] Such as figure 2 As shown, the first model includes at least:

[0075] From the gate terminal to the source and drain terminals, the parasitic inductance L of the gate terminal lead is connected in series g , Gate terminal lead resistance R g , channel capacitance C in , channel resistance R in , source-drain termination lead resistance R ds , source-drain termination lead parasitic inductance L ds ;

[0076] The channel capaci...

Embodiment 2

[0094] This embodiment provides a parameter extraction method for extracting parameters of the SOI-MOSFET model in Embodiment 1. The parameter extraction method includes parameter extraction of the first model and parameter extraction of the second model.

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Abstract

The invention provides an SOI-MOSFET model and a parameter extracting method thereof. The model comprises a first model body and a second model body. The first model body is a substrate parasitic model body, and the second model body is an MOSFET model body with a substrate parasitic network removed. According to the SOI-MOSFET model, substrate parasitic network model parameters and MOSFET parameters outside a substrate can be analyzed and extracted, and the extracting method is simple and easy to operate. According to the measuring and model simulation result, the model extracted through the method and an SOI-MOSFET working within the 20 GHz frequency range are good in goodness of fit; in addition, the relation between the substrate parasitic effect and the dimensions of devices can be calculated according to the substrate parasitic parameter values and optimized values of device models of different dimensions. The first model is suitable for the SOI-MOSFET devices of all the dimensions.

Description

technical field [0001] The invention relates to the field of circuit modeling, in particular to an SOI-MOSFET model and a parameter extraction method thereof. Background technique [0002] With the development of integrated circuits into today's deep sub-micron era, to further increase the integration level and operating speed of the chip, the existing bulk silicon materials and processes are approaching the physical limit of the device, and encounter severe challenges in reducing the feature size , Therefore, new major breakthroughs must be made in materials and processes. In the SOI process, the material forms a semiconductor thin film on the insulator, which has incomparable advantages over bulk silicon. It can realize the dielectric isolation of components in integrated circuits and completely eliminate the parasitic latch effect in bulk silicon CMOS circuits. Integrated circuits made of this material also have the advantages of small parasitic capacitance, high integra...

Claims

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Application Information

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IPC IPC(8): G06F17/50
Inventor 刘军田犁
Owner SHANGHAI ADVANCED RES INST CHINESE ACADEMY OF SCI
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