Method and device for manufacturing 3D cryptographic chip resisting fault injection attacks

Abstract

The invention provides a method and a device for manufacturing a 3D cryptographic chip resisting fault injection attacks, and relates to the technical field of safety of the 3D cryptographic chip. The method comprises the following steps of: determining a sensitive logical unit in a cryptographic circuit according to a fault injection attack method corresponding to a cryptographic algorithm used for the cryptographic circuit; layering the cryptographic circuit in a 3D mode, dividing the sensitive logical unit into a middle layer of the 3D layers, and generating a 3D cryptographic circuit subjected to 3D layering; determining liable-to-overturn region type of the region, where the sensitive logical unit is, in the 3D cryptographic circuit according to charged particle mobility under the influence of TSV (Through Silicone Vias) and STI (Sallow Trench Isolation) in the 3D cryptographic circuit; respectively inserting corresponding sensors at locations of the sensitive logical units a PMOS liable-to-overturn region, a NMOS liable-to-overturn region or a random overturn region, and completing safety manufacturing of the 3D cryptographic chip. The method and the device provided by the invention solve the problem of poor resistivity of the current 3D cryptographic chip to the fault injection attacks.

Description

technical field [0001] The invention relates to the technical field of security of 3D cryptographic chips, in particular to a method and device for manufacturing a 3D cryptographic chip resistant to error injection attacks. Background technique [0002] At present, with the development of Through Silicon Vias (TSV) technology, the TSV technology is changing the interconnection lines of integrated circuits from planar to three-dimensional (3D), forming a three-dimensional interconnection structure. The space utilization of the three-dimensional interconnection structure is better than that of the planar structure, which essentially reduces the length of the interconnection line, shortens the delay and power consumption of the interconnection line, and thus reduces the delay and power consumption of the entire circuit. Cryptographic chips are a very important branch of the integrated circuit industry, and are widely used in occasions where sensitive information needs to be kep...

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Problems solved by technology

[0004] Embodiments of the present invention provide a method and device for manufacturing a 3D cryptographic chip resistant to error injection attacks, to solve the problem that the current 3D cryptographic chip manufacturing does not consider its security against error injection attacks, resulting in the current 3D cryptographic chip resisting errors The problem of weak ability to inject attacks

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