NUMA memory management fault tolerance method based on TLB-MISS
A memory management and processor technology, applied in memory systems, electrical digital data processing, instruments, etc., can solve problems such as booting and lack of low-level physical addresses
Active Publication Date: 2016-01-13
JIANGNAN INST OF COMPUTING TECH
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[0005] The technical problem to be solved by the present invention is to address the above-mentioned defects in the prior art, and propose a TLB-MISS-based NUMA memory management fault-tolerant method, thereby solving the problem of low OS Boot Issues When Segment Physical Addresses Are Missing
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[0020] In order to make the content of the present invention clearer and easier to understand, the content of the present invention will be described in detail below in conjunction with specific embodiments and accompanying drawings.
[0021] From a logical point of view, the memory used by the operating system has two aspects. One is the memory where the operating system kernel itself is located, and the other is the physical memory managed by the operating system that can be allocated. The operating system kernel itself is also composed of an executable file. When the processor boots, there will be a lower-level Bootloader code (a small program that runs before the operating system kernel runs) to load the kernel executable file into a fixed physical address area. Usually, both the Bootloader code and the kernel assume that the memory physical address where the kernel is located is fixed. When the physical address of this segment does not exist for some reason, a boot failure...
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The invention provides an NUMA memory management fault tolerance method based on TLB-MISS. The method comprises the steps that a processor is powered on to enter a processing entrance of a microcode; the on-site condition of memories is judged, and a difference value between a lowest address in physical addresses of the on-site memory and zero is calculated; the difference value is saved; all TLB entries in the processor are cleared; a virtual address entrance of a processor core is carried out to start to operate a processor core code; if processor TLM-MISS abnormity is triggered in the processor core code operating process, the processor enters a TLB-MISS abnormity processing entrance to carry out a TLB-MISS abnormity processing program; the corresponding relationship between a virtual address and the physical addresses is calculated in the TLB-MISS abnormity processing program according to the difference value, and a correct TLB entry is filled according to the corresponding relationship; the processor exits the TLB-MISS abnormity processing program, returns to the code triggering the TLB-MISS abnormity and carries out the code triggering the TLB-MISS abnormity again.
Description
technical field [0001] The invention relates to the technical field of processors, in particular to a TLB-MISS-based NUMA memory management fault tolerance method. Background technique [0002] When there are multiple memory nodes on a multi-core or multi-processor machine, one or some memory nodes may be unavailable due to memory controller chip or memory particle failure. If the processor storage controller does not have the ability to customize memory addresses, and The physical address of the memory is fixedly arranged according to the number of the memory controller chip or the location of the memory particles, and a hole in the memory address will be formed. [0003] NUMA (Non-Uniform Memory Access, non-uniform memory access) refers to a technology in which there are multiple memory nodes on a multi-core or multi-processor machine, and the access time from the processor to different memory nodes is different. [0004] The NUMA operating system generally provides manag...
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IPC IPC(8): G06F12/0837G06F12/0891
Inventor 王星焱郑岩黄高阳陈斐朱蕾
Owner JIANGNAN INST OF COMPUTING TECH