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Stacked package and reduction of standby current

A stacked packaging and electrical coupling technology, which is applied in the direction of circuits, electrical components, semiconductor devices, etc., can solve the problems of semiconductor memory such as long time

Active Publication Date: 2019-05-03
SK HYNIX INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The method of increasing the storage capacity of semiconductor memory requires more effort and expense as well as longer time

Method used

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  • Stacked package and reduction of standby current
  • Stacked package and reduction of standby current
  • Stacked package and reduction of standby current

Examples

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Embodiment Construction

[0014] Reference will now be made in detail to embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. Embodiments of the present invention relate to a stacked package, and more particularly, to a technique capable of reducing a standby current by blocking a current path during a standby mode of a multi-stacked chip. One embodiment of the present invention relates to a technique capable of reducing a standby current by blocking a current path during a standby mode of a multi-stacked chip. Hereinafter, a stack package according to an embodiment will be described with reference to various drawings.

[0015] see figure 1 , shows a block diagram illustrating a package-on-package according to one embodiment of the present invention.

[0016] The package-on-package according to one embodiment includes pads PAD1 on the chip 10...

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Abstract

The stack package includes: a plurality of chips each stacked with a plurality of layers; and a plurality of pads respectively formed on the plurality of chips. Each chip includes: a ground path unit configured to form a current path between a pad and a ground stage; a selection unit configured to selectively control a connection path electrically coupled to the pad according to a chip enable signal; and a controller configured to selectively control a connection between the selection unit and the ground path unit according to a control signal.

Description

[0001] Cross References to Related Applications [0002] This application claims priority from Korean Patent Application No. 10-2014-0067041 filed on June 2, 2014, the disclosure of which is hereby incorporated by reference in its entirety. Background technique [0003] Recently, in response to miniaturization and higher performance of electronic devices and increasing demand for mobile products, the demand for ultra-miniaturized and high-capacity semiconductor memories is rapidly increasing. In general, various methods for increasing the storage capacity of semiconductor memories have been widely used. First, one method for increasing the storage capacity of semiconductor memories is to increase the degree of integration of semiconductor chips. Second, another method for increasing the storage capacity of a semiconductor memory is to pack and assemble a plurality of semiconductor chips in a single semiconductor package. [0004] A method of increasing the storage capacity o...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L25/065H01L23/488
CPCH01L25/0657H01L2924/0002H01L2924/00
Inventor 金兑炫金谦
Owner SK HYNIX INC