Stacked package and reduction of standby current
A stacked packaging and electrical coupling technology, which is applied in the direction of circuits, electrical components, semiconductor devices, etc., can solve the problems of semiconductor memory such as long time
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[0014] Reference will now be made in detail to embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. Embodiments of the present invention relate to a stacked package, and more particularly, to a technique capable of reducing a standby current by blocking a current path during a standby mode of a multi-stacked chip. One embodiment of the present invention relates to a technique capable of reducing a standby current by blocking a current path during a standby mode of a multi-stacked chip. Hereinafter, a stack package according to an embodiment will be described with reference to various drawings.
[0015] see figure 1 , shows a block diagram illustrating a package-on-package according to one embodiment of the present invention.
[0016] The package-on-package according to one embodiment includes pads PAD1 on the chip 10...
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