A single edge pulse signal generator based on cnfet

Abstract

The invention discloses a CNFET-based single-edge pulse signal generator, comprising a first CNFET tube, a second CNFET tube, a third CNFET tube, a fourth CNFET tube, a fifth CNFET tube, a sixth CNFET tube and a seventh CNFET tube tube, the first CNFET tube, the third CNFET tube and the sixth CNFET tube are P-type CNFET tubes, the second CNFET tube, the fourth CNFET tube, the The fifth CNFET tube and the seventh CNFET tube are N-type CNFET tubes; the grid of the first CNFET tube, the grid of the second CNFET tube, the source of the third CNFET tube and the grid of the fourth CNFET tube are connected , the drain of the first CNFET, the drain of the second CNFET, the gate of the third CNFET and the gate of the fifth CNFET are connected, the drain of the third CNFET, the drain of the fourth CNFET, The gate of the sixth CNFET is connected to the gate of the seventh CNFET, the source of the fourth CNFET is connected to the drain of the fifth CNFET, and the drain of the sixth CNFET is connected to the drain of the seventh CNFET ; The advantage is that it has obvious characteristics of high speed and low power consumption.

Description

technical field [0001] The invention relates to a pulse signal generator, in particular to a CNFET-based single-edge pulse signal generator. Background technique [0002] As the basis of sequential circuits, flip-flops usually account for 20%-50% of circuit power consumption. High-performance flip-flops are conducive to speeding up the speed of integrated circuits and reducing circuit power consumption. Compared with the master-slave flip-flop, the pulse flip-flop can effectively reduce the delay between circuits, and the single-latch structure also greatly simplifies the circuit design. A dominant pulse flip-flop is composed of an independent pulse signal generator and a latch. As a separate part, the pulse signal generator can share the pulse signal with multiple dominant pulse flip-flops, thus effectively saving hardware overhead and reducing large-scale circuit power consumption. The design of the pulse signal generator in the dominant pulse trigger will affect the com...

AI Technical Summary

Problems solved by technology

Analysis of the single-edge pulse signal generator shows that the gate-grounded PMOS transistor M1 is always on, and a short-circuit path from the power supply VDD to the ground will be formed when the discharge path is turned on, which increases the short-circuit power consumption, resulting in The power consumption of the single-edge pulse signal generator is increased, and because it adopts a MOS tube design, its speed is also low due to the limitation of the characteristics of the MOS tube itself

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