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Memory cell array and its cell structure

A memory cell array and array technology, applied in the direction of electrical components, electric solid-state devices, circuits, etc., can solve the problem of memory cell application

Active Publication Date: 2018-07-27
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] Conventional ROM cell arrays using planar cell transistors inherently exhibit a huge horizontal package size in the plane of the substrate, thus imposing practical limits on the scaling of memory cells

Method used

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  • Memory cell array and its cell structure
  • Memory cell array and its cell structure
  • Memory cell array and its cell structure

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Embodiment Construction

[0034] The following disclosure provides a number of different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to limit the invention. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are in direct contact, and may also include that other components may be formed between the first component and the second component An embodiment such that the first part and the second part are not in direct contact. Additionally, the present invention may repeat reference symbols and / or characters in multiple instances. This repetition is for simplicity and clarity, and does not in itself indicate a relationship between the various embodiments and / or configurations descr...

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Abstract

The invention discloses a read-only memory (ROM) unit array and its unit structure. The ROM cell array is connected to a plurality of row bit lines and a plurality of column word lines and includes: a plurality of sub-unit arrays arranged along a column direction, each sub-unit array including a plurality of unit cell structures. Each unit cell structure includes: a cell base region defining a cell boundary, the region including an overlying OD layer having a wide block profile and defining a continuous common source node disposed on the substrate; disposed on the OD layer Above, a drain pad arranged to selectively connect a bit line; a vertical channel structure bridging between the drain pad and the OD layer; and vertically disposed between the drain pad and the OD layer and A gate structure arranged in connection with the word line. The subcell array boundaries are completely confined within the coverage of the OD layer.

Description

technical field [0001] The present invention relates generally to semiconductor memories and, more particularly, to semiconductor read only memory (ROM) cell array structures. Background technique [0002] Conventional ROM cell arrays using planar cell transistors inherently exhibit a large horizontal package size in the plane of the substrate, thus imposing practical limits on the scaling of memory cells. Therefore, memory cell arrays and cell structures thereof have been proposed. Contents of the invention [0003] According to one aspect of the present invention, there is provided a semiconductor read-only memory (ROM) unit cell structure, comprising: a cell base region defining a cell boundary, the unit base region comprising a wide-shaped block-shaped outline arranged on a substrate an overlay OD layer, and the overlay OD layer defines a continuous shared source node arranged to be selectively connected to the ground terminal (Vss); a drain pad, disposed on the OD la...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/112
CPCH01L29/7827H01L29/0676H10B20/40H10B20/00H10B63/34H01L29/66742H01L29/7841H01L29/78642
Inventor 廖忠志
Owner TAIWAN SEMICON MFG CO LTD