A Method of Instruction Dependency Detection in Superscalar Processor

Abstract

The invention discloses a method for detecting an instruction correlation in a superscalar processor. The method comprises: by setting a set of lock identifications and decoding an instruction, comparing a source operand and a target operand with a corresponding lock identification separately, and determining the correlation and parallelism of the instruction; updating the lock identifications according to instruction decoding information of each cycle, and updating once every cycle; and enabling the lock identifications to be in one-to-one correspondence with a general register group in a processor, wherein each register has a corresponding lock identification. The method disclosed by the present invention is not only applicable to detecting whether multiple instructions in a same cycle can be transmitted simultaneously, but also applicable to detecting the correlation among instruction groups in different pipeline stages; and the method provides a basic guarantee for realizing dynamic scheduling of the instruction, moreover, the implementation of the method does not relate to a very complex circuit design, so that the hardware overhead can be greatly reduced.

Description

Technical field [0001] The invention belongs to the technical field of processor architecture design, and specifically relates to a method for detecting instruction correlation in a superscalar processor. Background technique [0002] In superscalar processors, instructions are often issued, and the maximum number of instructions that can be issued in the same cycle depends on the width of the issue slot. In order to achieve instruction-level parallelism, the superscalar processor uses a dynamic scheduling method. In the sequential execution of instructions, in addition to the width of the launch slot, the data correlation between instructions has become an important factor restricting maximum instruction-level parallelism. Detecting whether there is data correlation between instructions in the same cycle is the key to dynamic instruction scheduling. Pipeline technology is often used in the architecture design of superscalar processors. After the instruction level is paralleliz...

AI Technical Summary

Problems solved by technology

This detection method is indeed feasible, but the cost of hardware overhead is relatively high. If there are many operands, the area of ​​the module will be greatly increased, which will cause power consumption problems, and related logic will take up a lot of resources.

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