Memory testing method for reducing cache hit rate

A cache hit rate and memory testing technology, applied in the field of memory testing to reduce cache hit rate, can solve problems such as the impact of test effectiveness, and achieve the effects of improving effectiveness, optimizing memory testing methods, and reducing cache hit rate.

Active Publication Date: 2016-03-02
INVENTEC PUDONG TECH CORPOARTION +1
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

The current diag program on the market has not made effective optimization and targeted treatment for this problem, so the effectiveness of the test will be affected to a certain extent

Method used

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  • Memory testing method for reducing cache hit rate
  • Memory testing method for reducing cache hit rate
  • Memory testing method for reducing cache hit rate

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Embodiment Construction

[0017] Embodiments of the present invention will be described below with reference to the drawings. Elements and features described in one drawing or one embodiment of the present invention may be combined with elements and features shown in one or more other drawings or embodiments. It should be noted that representation and description of components and processes that are not related to the present invention and known to those of ordinary skill in the art are omitted from the drawings and descriptions for the purpose of clarity.

[0018] figure 1 It is a flowchart of a memory testing method for reducing a cache hit rate provided by an embodiment of the present invention.

[0019] Such as figure 1 As shown, in this embodiment, the memory test method for reducing the cache hit rate provided by the present invention includes:

[0020] S10: Divide the memory to be tested into several memory segments with preset sizes;

[0021] S30: Divide the preset memory test algorithm int...

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Abstract

The invention provides a memory testing method for reducing a cache hit rate. The method comprises: dividing a to-be-tested memory into a plurality of memory sections of preset sizes; dividing a preset memory testing algorithm into a plurality of testing steps; and performing the testing steps on the memory sections in sequence, wherein one testing step is performed on another memory section between any two continuous testing steps performed on each memory section. According to the method, the testing steps are performed on different memory sections in sequence, so that a cache cannot continuously form effective concerned sections, the cache is always in a shake state, the cache hit rate is reduced, and the validity of memory testing is improved; and further, execution time and cache hit of an execution process of the memory testing algorithm are subjected to monitoring and statistics, and testing step division of the memory testing algorithm is optimized according to a statistic result, so that the efficiency and validity of memory testing are both considered and the memory testing method is optimized.

Description

technical field [0001] The invention relates to the technical field of memory testing, in particular to a memory testing method for reducing cache hit rate. Background technique [0002] The validity of the memory test has always been a very important criterion for measuring the quality of the test, especially for the diag program in the integration test stage. Today's processors have multi-level caches (cache), and the size of each level of cache is gradually increasing with the advancement of technology. At present, high-end Intel processors are basically divided into three levels of cache, and the third level cache The cache size has reached 4M or even larger. Therefore, in the memory test, how to effectively and ensure that each read and write operation is actually operated on the memory instead of falling into the multi-level cache is a very important issue. The current diag program on the market has not made effective optimization and targeted treatment for this prob...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/26
Inventor 李岩
Owner INVENTEC PUDONG TECH CORPOARTION
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