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Semiconductor chip structure to be cut and its manufacturing method

A chip structure and semiconductor technology, applied in the direction of semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., can solve the problems of increasing the manufacturing cost of semiconductor chip manufacturing process, avoid damage, reduce production cost, process simple effect

Active Publication Date: 2018-09-18
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the change in the structure of the sealing ring will inevitably lead to an increase in the manufacturing cost of the semiconductor chip manufacturing process.

Method used

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  • Semiconductor chip structure to be cut and its manufacturing method
  • Semiconductor chip structure to be cut and its manufacturing method
  • Semiconductor chip structure to be cut and its manufacturing method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0056] Such as Figure 5 with Image 6 As shown, in Embodiment 1, the semiconductor chip structure to be cut includes a semiconductor substrate 20, and a plurality of semiconductor chips 21 are formed on the semiconductor substrate 20; a scribe line 22 is formed between two adjacent semiconductor chips 21, in order to facilitate cutting , the cutting road 22 includes two groups of cutting roads 22 perpendicular to each other in the horizontal extension direction, and the cutting roads 22 in each group of cutting roads 22 are parallel to each other;

[0057] Each semiconductor chip 21 includes an integrated circuit area 21a, a sealing ring 23 arranged around the integrated circuit area 21a; Interlayer dielectric layer 24b between interconnection lines 24a;

[0058] The passivation layer 25 is formed on the surface of the integrated circuit region 21a, the surface of the sealing ring 23 and the surface of the scribe line 22, and a groove 26 is formed in the passivation layer 2...

Embodiment 2

[0063] pass Figure 8 Embodiment 2 in the present invention will be described. Figure 8 The cross-sectional structure of the semiconductor device to be diced according to the present embodiment is shown, and the same reference numerals are given to the parts common to the first embodiment.

[0064] exist Figure 8 In the semiconductor device to be cut in the present embodiment 2 shown, passivation remains between the bottom of the groove 26 in the passivation layer 25 on the surface of the dicing line 22 between two adjacent semiconductor chips 21 and the surface of the dicing line 22. layer 25', the other parts are the same as the structure of the first embodiment, and can obtain the same effect as the first embodiment.

[0065] Based on the second embodiment, since the passivation layer 25' remains between the bottom of the groove 26 and the surface of the scribe line 22, when cutting the semiconductor chip, the shear stress needs to overcome the adhesion force in the fir...

Embodiment 3

[0067] pass Figure 9 Embodiment 3 in the present invention will be described. Figure 9 The planar structure of the semiconductor device to be diced according to the present embodiment is shown, and the same reference numerals are given to the parts common to the first embodiment.

[0068] Such as Figure 9 As shown, in the semiconductor device to be cut in the third embodiment, the horizontal extension direction of the groove 26' in the passivation layer 25 on the surface of the cutting line 22 between two adjacent semiconductor chips (not marked) is the same as that of the cutting line. The horizontal extension direction of the road 22 is vertical, and the other parts are the same as the structure of the first embodiment.

[0069] In the third embodiment, since the horizontal extension direction and the horizontal extension direction of the trench 26' in the passivation layer 25 are perpendicular to the horizontal extension direction of the cutting line 22, when subjected...

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PUM

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Abstract

The invention provides a to-be-cut semiconductor chip structure and a manufacturing method thereof. According to the invention, a passivation layer between the cutting surfaces of every two adjacent semiconductor chips is internally provided with at least one trench. When a shear stress is applied on the structure, the passivation layer with the trench deforms or even wraps preferentially under the action of the stress. In this way, the shear stress is released, so that the torque of the shear stress, transmitted to the semiconductor chips, is reduced. Meanwhile, the damage of the shear stress to the semiconductor chips is avoided.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a semiconductor chip structure to be cut and a manufacturing method thereof. Background technique [0002] In the manufacture of a semiconductor process, a semiconductor chip is formed on a semiconductor substrate. Such as figure 1 As shown, a single semiconductor substrate 10 may contain a plurality of substantially identical semiconductor chips 11 , and each semiconductor chip 11 is generally substantially rectangular and arranged in rows and columns. Two sets of dicing lines 12 perpendicular to each other extend between the discrete semiconductor chips 11 , wherein each set of dicing lines 12 are parallel to each other. [0003] Such as figure 2 with 3 As shown, each semiconductor chip 11 to be cut includes an integrated circuit area 11a, a sealing ring 13 arranged around the integrated circuit area, and a passivation layer 15, and the passivation layer 15 is forme...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/16H01L23/522H01L21/56H01L21/60
Inventor 王晓东
Owner SEMICON MFG INT (SHANGHAI) CORP