CRC verification circuit and verification method suitable for 64-bit bus width

Abstract

The present invention provides a CRC (Cyclic Redundancy Check) checking circuit applicable to 64-bit bus bit width and a checking method, and can achieve a purpose of reducing the number of CRC-16 checkers only by means of 16-bit and 64-bit parallel CRC checkers plus an equivalent logic structure of delay determination and bitwise negation for transaction packet data in 16-bit, 32-bit, 48-bit and 64-bit alignment formats. The CRC-16 checking circuit provided by the present invention not only can implement checking of transaction packets in different sizes and different formats, but also is obviously improved in terms of area, power consumption and speed.

Description

technical field [0001] The invention relates to the field of high-speed serial interfaces, in particular to a CRC check circuit and a check method suitable for 64-bit bus width. Background technique [0002] The protocol of the physical layer of the high-speed serial interface stipulates that the transaction packet transmitted from the logical layer to the physical layer needs to pass through the cyclic redundancy check (Cyclic Redundancy Check, CRC) code generation circuit of the physical layer to generate a 16-bit CRC before sending out. checksum. At the receiving end, the receiving circuit of the physical layer needs to check the CRC code of the received transaction packet, and confirm whether the received transaction packet has an error on the transmission link by judging the correctness of the CRC code, so as to achieve the purpose of protecting data . [0003] General high-speed interfaces, such as RapidIO2.1, PCIE2.0 and USB3.0, all use CRC-16 check type, and the ge...

AI Technical Summary

Problems solved by technology

Although the speed can be improved, but the area is larger, more resources are occupied, and the power consumption is larger

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