FPGA-based device and method for loading and upgrading object codes

Abstract

The invention discloses an FPGA-based device and method for loading and upgrading object codes. The device comprises a main control processor, an FPGA, a bidirectional buffer having the output enable control, and a non-volatile memory. The FPGA and the non-volatile memory are connected via four data signal lines, one clock signal line and one chip selection signal line. The main control processor and the non-volatile memory are connected, and the bidirectional buffer is arranged between the main control processor and the non-volatile memory for isolating switch. The main control processor also controls the output enable of the bidirectional buffer and the initial reset signal of the FPGA. Based on the above method and the above device, not only the upgrading function is realized, but also the loading rate of the FPGA is ensured. Meanwhile, the start-up time of the system is reduced.

Description

technical field [0001] The invention relates to the field of data communication, in particular to a device and method for loading and upgrading target codes of FPGA. Background technique [0002] FPGA (Field Programmable Gate Array, Field Programmable Gate Array) is widely used in communication due to its advantages of parallel operation of internal logic, high-speed working clock, rich input and output pin resources, integrated high-speed serial transceiver module, and core resources of specific interface protocols. In the hardware equipment system, functions such as board-level logic control, interface conversion, data transmission, and algorithm processing are completed. Based on the characteristics of chips such as FPGA, the target code will be lost when the system is powered off, so the target code needs to be stored in the non-volatile memory outside the chip during system design, and the FPGA will be loaded every time the system starts. Operation of the object code. ...

AI Technical Summary

Problems solved by technology

The disadvantages of this mode are: 1. The content in the non-volatile memory is updated by the FPGA itself. If the wrong object code is obtained or the system is powered off during the update process, the incomplete or incorrect object code will be lost. Overwrite the original correct object code of the non-volatile memory, when the system restarts, the FPGA cannot work normally, and the FPGA object code cannot be upgraded again (unless other tools such as an emulator are connected), which will become a serious problem. System defects and hidden dangers; 2. The data transmission rate of the single-wire serial interface is low, which leads to a long loading time of the FPGA and increases the startup time of the entire system

This implementation scheme has system defects and hidden dangers, as well as long FPGA loading time and other deficiencies.

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