A decoding circuit of a power instruction set vector coprocessor

Abstract

The invention relates to a decoding circuit for a POWER instruction set vector coprocessor. The input end of a first judger is connected to the output end of a main processor and used for receiving an instruction and judging whether the instruction is an effective instruction or not; the output of a first setter is connected to the input end of the main processor and used for feeding back the fact that the instruction is effective or ineffective to the main processor, enabling the effective marking position of the instruction of the vector coprocessor to be high when the effective instruction information of the first judger is received, otherwise, enabling the effective marking position of the instruction of the vector coprocessor to be low, and sending to a second judger; the input end of the second judger is connected to the output end of the main processor; after the effective information of the first setter is received, the data source of operation data required for a function execution unit and a functional unit, which the instruction belongs to, is judged and sent into a second setter; and the second setter sends a control signal corresponding to a judging result of the second judger and the operation data to be read by the instruction to different function execution units. According to the invention, the required judging logic is simpler when the functional unit identifies the specific instruction type of the received instruction.

Description

technical field [0001] The invention relates to a decoding circuit. In particular, it relates to a decoding circuit of a POWER instruction set vector coprocessor. Background technique [0002] SIMD (Single Instruction Multiple Data) is a data-level parallel technology that performs the same operation on multiple data. The key to SIMD technology is to perform multiple operations simultaneously in a single instruction to increase the throughput of the processor. This feature makes SIMD technology especially suitable for data-intensive operations such as multimedia applications. Now mainstream processors have their SIMD instruction subsets, such as MMX or SSE of X86, NEON instruction subset of ARM, Altivec instruction subset of PowerPC, etc. In modern multi-core processors, each core on the processor is usually equipped with a dedicated SIMD coprocessor, also known as Vector Coprocessor (VP). As a key part of the overall performance of the coprocessor, the first-level decodi...

AI Technical Summary

Problems solved by technology

The entire decoding process is equivalent to a process of encoding first and then decoding, resulting in a waste of resources and an increase in power consumption

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