Reconfigurable Cryptographic Processor

Abstract

The present invention discloses a reconfigurable cryptographic processor. The reconfigurable cryptographic processor is characterized by comprising: a configuration module, for acquiring and assigning a configuration parameter; a transmission module, for transmitting to-be-processed data according to the assigned configuration parameter; a processing module, for obtaining processed data and transmitting the processed data to the transmission module to output, wherein the processing module comprises an array operation cache for storing intermediate data and interaction data; a reconfigurable array, for realizing the operation, wherein each reconfigurable unit has a token driver enabling end for token enabling; and an asynchronous driver enabling network, for obtaining a token enabling network according to the assigned configuration parameter to provide a data jumping and transmission mode of the operation and to complete driving of the reconfigurable array, so as to control the reconfigurable cryptographic processor to enter into a corresponding working mode. According to the reconfigurable cryptographic processor provided by the embodiment of the present invention, the driver execution process is enabled by using the token, so that flexibility and execution performance are improved, power consumption is reduced, and security and reliability are better ensured.

Description

technical field [0001] The invention relates to the field of electronic technology, in particular to a reconfigurable cryptographic processor. Background technique [0002] In recent years, the security situation of information systems has become more and more severe, and more stringent requirements have been put forward for the flexibility, speed, power consumption and security of cryptographic processor chips. The current cryptographic processor chips can be mainly divided into two categories in terms of architecture and design methods. The first category is the implementation of ASIC (Application Specific Integrated Circuit, Application Specific Integrated Circuit), and the second category is the implementation of instruction set architecture microprocessor (ISAP). The ASIC implementation often optimizes the algorithm, so the operation speed is far faster than the ISAP implementation. However, after the design is completed, the hardware structure cannot be changed, which...

AI Technical Summary

Problems solved by technology

Due to the use of pipeline technology, the processor can only work in synchronous timing, so that the processor cannot perform optimally, and at the same time increases the possibility of the processor being physically attacked (such as power consumption attack).

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