Thin film transistor and its preparation method, array substrate and its preparation method, and display device

Abstract

The invention belongs to the display technical field, and relates to a thin film transistor (TFT) and a preparation method, an array substrate and a preparation method, and a display device. The TFT comprises a grid, a gate insulation layer, a source, a drain electrode and an active layer, wherein the drain electrode, the active layer and the source are successively laminated; the orthographic projection area of the active layer on the plane parallel with the drain electrode is the same with the area of the drain electrode; the orthographic projection area of the source on the plane parallel with the drain electrode is less than the area of the drain electrode; the gate insulation layer is at least partially in contact with the active layer; the grid is arranged outside the gate insulation layer and covers the side surface and partial top surface of the gate insulation layer away from the source. The TFT can obtain high starting current under low resistance in an open state, minimize off-current in a closure state, and effectively inhibit off-current.

Description

technical field [0001] The invention belongs to the field of display technology, and relates to a thin film transistor, a preparation method, an array substrate, a preparation method and a display device. Background technique [0002] A thin film transistor (Thin Film Transistor: TFT for short) is a common semiconductor device, especially used in the field of display technology. With the development of display technology, TFT-LCD (Liquid Crystal Display: liquid crystal display device), as a flat panel display device, is more and more used in high-performance displayed in the field. [0003] In the field of display technology, none of the developments from TN technology to IPS technology to FFS (ADS, HADS) technology can be separated from the control of thin film transistors. The on and off states of thin film transistors are usually controlled by the gate voltage, and an inversion layer (conductive trench) is formed in the active layer near the gate, and the carriers pass ...

AI Technical Summary

Problems solved by technology

Compared with BJT, CMOS and other devices (electrode coplanar structure), the conductive trench in the existing back trench etched bottom gate a-Si TFT is formed at the lower interface of the semiconductor layer close to the gate, while the source 9 / The drain 3 is located above the semiconductor layer, therefore, the flow of carriers must first pass through the thickness of the semiconductor layer of the non-inversion layer with poor conductivity and then enter the inversion layer region, which seriously affects the conductivity of the device

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