Method and system for reducing packet forwarding delay

Abstract

The invention provides a method and a system for reducing packet forwarding delay. The method comprises the steps of receiving data from each data channel, and storing the data into a first level cache; generating a first level scheduling request command and / or a first level analysis request command for the data in the first level cache according to the current storage state of the first level cache and attribute information carried by the data; if the first level scheduling request command is received, uploading all data in the current first level cache to a first level scheduling cache; if the first level analysis request command is received, analyzing the data in the current first level cache, and storing the analysis result into the first level analysis cache; matching the data stored in the first level scheduling cache with the analysis result of the data stored in the first level analysis cache, and determining whether second-level scheduling is to be performed on the current data according to the attribute and matching result of each data. According to the method and system, the packet forwarding delay is reduced.

Description

technical field [0001] The invention relates to the field of network communication, in particular to a method and system for reducing message forwarding delay. Background technique [0002] Transmission delay is one of the key parameters of network chips, and low delay is an important reference performance for network chip design. In a high-density network chip, multi-channel data is aggregated to the data receiving module and dispatched to the chip for processing, and finally the data processing results are stored together with the data itself in the data storage module. [0003] Traditional processing procedures such as figure 1 As shown, the data receiving module is externally connected to multiple data channel groups, and the control and storage logic between the channel groups are independent of each other; each data channel group contains multiple data channels, and the bit width of the data channel is W. Each data channel group uses A piece of 1-read 1-write memory ...

AI Technical Summary

Problems solved by technology

[0006] T total delay = T data aggregation + T data receiving module internal delay + T message analysis module internal delay + T data storage module internal delay; through the analysis of the above architecture, the data forwarding delay in the existing architecture longer time

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