Measuring circuit of data establishing time of D triggers

Abstract

The invention discloses a measuring circuit of data establishing time of D triggers. The measuring circuit comprises m D triggers. Data input ends of the D triggers are connected with data input signals. Q output ends and Q NOT-output ends of the D triggers output m positive and negative phase data output signals. The clock input end of the kth D trigger is connected to a clock input signal via k+1 data buffers. During measurement, when the positive phase data output signals of Q output ends of all the D triggers are in '0' states, the data input signals are switched to the '1' state from the '0' state and the clock input signals change along with the data input signals. By reading numbers in the '0' state in m positive phase data output signals or numbers in the '1' state in m negative phase data output signals, the number is multiplied by the time delay of the data buffer so that the data establishing time of the D triggers is obtained. According to the invention, precise measurement of the data establishing time of the D triggers can be achieved.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit, in particular to a measurement circuit for the data establishment time of a D flip-flop (DFF). Background technique [0002] Such as figure 1 As shown, it is a schematic diagram of the data setup time (setup) of the D flip-flop; the D end of the D flip-flop 101, that is, the data input end, is connected to the data input signal DATA, and the clock input end is connected to the clock input signal CLOCK. When the clock input signal CLOCK rises Edge, the Q output terminal or Q non-output terminal of the D flip-flop 101 will switch data according to the data input signal DATA, but a realization condition is that the data input signal DATA must be before a data setup time from the rising edge of the clock input signal CLOCK It remains stable, and the signal that changes during the data setup time before the rising edge of the clock input signal CLOCK will not be output. [0003] exist figure 1 ...

AI Technical Summary

Problems solved by technology

However, the data establishment time of the D flip-flop is generally on the order of ps, and it is difficult to measure directly

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