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Multi-core heterogeneous system translation lookaside buffer coherency

A buffer and backup technology, applied in the field of multi-core heterogeneous system conversion backup buffer coherence, can solve the problems of coherent identification processing time and high power consumption

Active Publication Date: 2016-06-01
QUALCOMM INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

The TLB can use a many-to-one mapping of virtual pages to physical pages in system or common memory, making coherent identification of entries expensive in terms of processing time and power consumption

Method used

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  • Multi-core heterogeneous system translation lookaside buffer coherency
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  • Multi-core heterogeneous system translation lookaside buffer coherency

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Embodiment Construction

[0014] Various aspects will be described in detail with reference to the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. References made to particular examples and implementations are for purposes of illustration, and are not intended to limit the scope of the invention or the claims.

[0015] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any implementation described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other implementations.

[0016] The terms "computing device" and "multi-core heterogeneous computing device" are used herein to refer to cellular phones, smart phones, equipped with at least a first processor (or first processing unit) and a second processor (or second processing unit) (e.g., iPhone), web tablets, tablet computers, Internet-enabled cellular phones, WiFi-enabled ele...

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Abstract

Methods, devices, and instructions for performing a reverse translation lookaside buffer (TLB) look-up using a physical address input, including obtaining with a first processor the physical address input, wherein the physical address input indicates a physical address corresponding to a shared memory, obtaining a first mask associated with a first virtual address from a first TLB entry within a TLB associated with the first processor, wherein the obtained first mask is a bit pattern, obtaining from the first TLB entry a first page frame number associated with the shared memory, applying the obtained first mask to the obtained first page frame number to generate a first value, applying the obtained first mask to the obtained physical address input to generate a second value, and comparing the first value and the second value to determine whether the first value and the second value match.

Description

Background technique [0001] Computing devices typically include many processors for executing various instructions / systems. For example, a smartphone mobile device may utilize an applications processor to perform routines associated with downloaded applications and a digital signal processor to perform signaling processing operations. Such processors can each be configured to utilize a virtual memory address scheme so their respective processes can access data using simplified memory addresses that map to various physical addresses within system memory. For example, an application processor can utilize contiguous virtual addresses to access arbitrary RAM locations associated with data for the application. [0002] Devices are now starting to take advantage of various processors of different architectures. Such heterogeneous systems can increase the potential for software to benefit from shared memory, and can utilize various application programming interfaces (APIs) such as ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/1009G06F12/1036
CPCG06F12/1009G06F12/1036G06F2212/656G06F2212/683G06F12/1027
Inventor J·沈L·G·蔡-奥恩
Owner QUALCOMM INC